An 8-bit 10-GHz 8 × time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporates an aggressively scaled digital-to-analog converter (DAC) with grouped capacitors in a symmetrical structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A detailed study rigorously analyzes the effect of gradient on the proposed DAC layout. The DAC additionally implements quantized sub-radix-2 scaling with redistributed redundancy. A high-speed dual-path bootstrapped switch decouples the critical signal from the nonlinear parasitic capacitance to boost the sampling spurious-free dynamic range (SFDR) by more than 5 dB. Fabricated in a 28-nm CMOS process, the ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding a figure-of-merit of 37 fJ/conv.-step, the best among state-of-the-arts.

LED drivers for automotive lighting applications adopt Pulse Width Modulation (PWM) vis-à-vis Pulse Frequency Modulation because its ensuing Electro-Magnetic Interference (EMI) spectrum is predictable and easily mitigated. Nevertheless, present-day PWM control schemes adopted in LED drivers suffer from imprecise output current and subharmonic oscillation, which compromises reliability. In this paper, we present a PWM-based LED driver that features low EMI and high reliability. These attributes are achieved by our proposed Average Current Control (ACC), proposed accuracy-enhanced on-chip current sensors, and our adoption of a dual-phase power stage. The ACC eliminates subharmonic oscillation by means of considering the complete inductor-current profile vis-à-vis peak current adopted elsewhere. Also by means of the dual-phase power stage, good current balance and small current ripple are obtained. Collectively, the aforesaid substantially improves the reliability. To improve Electro-Magnetic Compatibility (EMC), the proposed accuracy-enhanced on-chip current sensors are monolithically realized with the ACC and power transistors – to the best of our knowledge, the first for a PWM-based dual-phase LED driver. The prototype LED driver, realized in a 130nm BCDLite process, has an input voltage range of 5-16V, output to drive 1-3 series-connected LEDs, provides a current regulation accuracy of at least 96.2%, dimming frequency up to 20kHz, features a peak power-efficiency of 94.7%, settling time of 5μs, LED current range of 0.4-2.4A and current-ripple factor of 8%. When benchmarked against the state-of-the-art LED drivers, our design features the highest peak power-efficiency, the shortest settling time, highest current driving capability, and the lowest current-ripple factor.

The purpose of this paper is to investigate the short-term wind power forecasting. STWPF is a typically complex issue, because it is affected by many factors such as wind speed, wind direction, and humidity. This paper attempts to provide a reference strategy for STWPF and to solve the problems in existence. The two main contributions of this paper are as follows. (1) In data preprocessing, each encountered problem of employed real data such as irrelevant, outliers, missing value, and noisy data has been taken into account, the corresponding reasonable processing has been given, and the input variable selection and order estimation are investigated by Partial least squares technique. (2) STWPF is investigated by multiscale support vector regression (SVR) technique, and the parameters associated with SVR are optimized based on Grid-search method. In order to investigate the performance of proposed strategy, forecasting results comparison between two different forecasting models, multiscale SVR and multilayer perceptron neural network applied for power forecasts, are presented. In addition, the error evaluation demonstrates that the multiscale SVR is a robust, precise, and effective approach.

Conventional LED matrix drivers for automotive Adaptive Driving Beam (ADB) headlighting drive a serial-connected LED matrix, hence resulting in two power-conversion stages, low power-efficiency, and large current ripples. This paper presents a monolithic parallel-connected LED matrix driver. It exhibits a high power-efficiency (94.8%) because of only one power-conversion stage, and achieves substantially small LED current-ripple factor (5%). Attributed to the proposed $I^{2} V^{2}$ controller, good current balance between dual phases, accurate LED current regulation and fast transient response are achieved.

This paper describes a 10-bit 5-kHz SAR ADC under an ultra-low-supply-voltage of 0.2 V for low-power applications. To tolerate the severe variations in the subthreshold regime, a novel dynamic bulk biasing circuit senses the NMOS/PMOS strength ratio in the background and applies feedback to equalize the strengths to maintain the circuit functionality. A rigorous analysis examines the dynamics and convergence of the proposed biasing circuit in the time-and $z$ -domains. A new comparator relaxes the stringent speed-noise trade-off under the 0.2-V supply. Employing switched ac-coupling, stacked input pairs, and voltage-boosted load capacitors, the comparator achieves more than a threefold improvement in speed with little noise penalty. The DAC implements grouped capacitors with quantized sub-radix-2 scaling for redundancy and low power and achieves 10-bit matching. Details of the complete ADC design are described. The measured ADC consumes 22 nW and exhibits a peak DNL and INL of 0.45 LSB and 0.67 LSB, respectively. The measured SFDR and SNDR at Nyquist are 70.6 dB and 52.8 dB, respectivley, yielding an FoM of 12.3 fJ/conv.-step. Measurements show the dynamic bulk biasing compensates the N/P strength ratio variations to optimize the SNDR. We also show that the proposed dynamic bulk biasing successfully maintains the ADC performance over supply variations and improves the yield by nearly twofold over 20 chips.

Present universal serial bus (USB) battery chargers often suffer from limitations to meet the increasing demand for quick charging due to compromised power efficiency and complicated hardware implementation. In this paper, we propose a charge unifiable (QU) control scheme that enables a battery charger to improve power efficiency in a low-profile hardware manner. This scheme features fully soft-switching (vis-à-vis hard switching) and single control scheme (vis-à-vis multiple) for distinct constant current (CC) and constant voltage (CV) charging modes. To the best of authors' knowledge, the proposed QU control scheme is the first to simultaneously offer fully soft-switching, innate CC-and-CV regulation, and seamless CC-to-CV transition. To verify the proposed design, we monolithically realize a low-profile high-efficiency fast battery charger based on this scheme. The prototype embodying a tiny 470-nH output inductor supports a maximum input voltage of 16V, output voltage of 2.2-4.2 V, output current of 0.1-2 A, and peak power efficiency of 96.2%. When benchmarked against state-of-the-art counterparts, the proposed charger features at least 2.1x smaller inductor and 7.2% higher power efficiency at both the maximum and the minimum output power charging scenarios. Further, this charger is the only design that features ≥ 91% power efficiency in the whole load range.