A three-dimensional (3-D) integration technology involving the use of a through-silicon-via (TSV) offers advantages such as low power consumption, small form factor, and large bandwidth. However, owing to the incompleteness of the 3-D manufacturing process, TSVs may exhibit some inherent defects; hence, switching and shifting repairing methods have been proposed. These methods repair the TSV faults by rerouting the signals of the faulty TSVs to the other signal TSVs or redundant TSVs using a simple repair algorithm. However, if one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the FTSV increases, i.e., the TSV defects tend to be clustered. Therefore, recently proposed repair solutions, such as ring/router-based repair architectures, have focused on clustered TSV faults. However, the implementation of these existing repair solutions for clustered faults involves an extremely high hardware overhead. This study proposes a TSV redundancy architecture to repair clustered TSV faults with a high repair rate and low hardware overhead. The proposed architecture divides the TSVs into several groups and connects the TSVs of each group using a 2:1 multiplexer chain. Simulation results show that the proposed architecture exhibits a repair rate of 98.52% for uniformly distributed faults and 69.86% for highly clustered faults. These repair rates are higher than those of other TSV redundancy architectures and the difference in the repair rate becomes even greater if the faults are more clustered. Moreover, the approach yields a 58.55% reduced area as compared to that of the router-based redundancy architecture, which also targets the repair of clustered faults.

Recently, three-dimensional integrated circuit (3-D IC) design has attracted much attention, and the reliability of these systems has become increasingly important. In this paper, a new repairable and reliable through-silicon via (TSV) set structure is proposed. This proposed TSV set structure can be applied to the previous TSV repair structures which require TSV redundancies, and detects a defect or error reutilizing residual TSV redundancies for high reliability of 3-D ICs. Both online test and soft error detection/analysis are supported by the proposed approach. Furthermore, a redundancy-sharing structure is introduced to guarantee a balanced detection rate among TSV sets and a reasonable full detection rate. The experimental results prove that the new approach guarantees high redundancy utilization efficiency and reliability of TSV. Also, they show that defect or error detection is achieved by the proposed TSV set structure.

Three-dimensional integrated circuits (3D ICs), which feature many benefits such as high bandwidth and a high degree of integration, have recently received considerable attention from the semiconductor industry. However, these chips feature through-silicon vias (TSVs), which vertically connect multiple dies, and these TSVs may fail, resulting in a decreased yield. Unfortunately, previously proposed methods to repair TSVs cannot handle certain failure patterns. For example, existing techniques cannot repair clustered TSV faults, which commonly occur in practice. Furthermore, the number of signal TSVs typically determines the number of redundant TSVs, which may result in wasteful and redundant TSVs. In this paper, a new TSV repair scheme is proposed that replaces defective TSVs with redundant TSVs by utilizing the architecture of a cube, which can replace any face with any of the other faces. Both signal TSVs and redundant TSVs are placed in the face of cube, so any faulted TSVs can be replaced with redundant TSVs. The experimental results indicate that the new method guarantees 100% coverage with any number of signal TSVs and redundant TSVs.

Three-dimensional integrated circuits (3-D ICs) utilizing through-silicon via (TSV) technology have many advantages over 2-D ICs, including high bandwidth, high density, and low power consumption. However, TSV, which is a key feature of 3-D ICs, has not only problems due to defects in the manufacturing process but also potential problems due to aging. Various solutions have been proposed to address each of these issues, but no one solution has been proposed considering both. In practice, to improve the overall reliability of the TSV, the two problems should be solved together, not separately. In this article, a new TSV architecture is proposed to cope with both issues. The proposed TSV architecture uses redundant TSVs (RTSVs) to repair faulty TSVs due to manufacturing defects and uses unused RTSVs in this way to solve the aging-related problems. Experimental results show that the proposed architecture achieves similar repair rate with less than 1% difference in less than six clustered faults using smaller hardware overhead, and also shows that unused RTSVs are available with a 98.5% high probability, resulting in a 1.5 times improvement in lifetime.

Test-point insertion (TPI) is an effective technique for improving the random pattern testability of digital circuits. However, it introduces area and performance overhead. Because the test-point area takes a significant portion of the test logic area, many techniques have been studied to reduce the area impact, such as sharing a control point (CP) driver with multiple CPs or replacing a dedicated CP driver with an existing flip-flop. This article proposes shared point insertion for area overhead reduction (SPAR) to simultaneously reduce the area impact of CPs and observation points (OPs). SPAR inserts a shared point instead of inserting a pair of CP and OP individually. Consequently, the pair of CP and OP is provided requirements, such as a control signal or propagation path from each other through the shared point—accordingly, the shared point simultaneously functions as the CP and OP. Furthermore, a signal that drives a shared point can be chosen to ensure the fair propagation of faults. The proposed flow searches for appropriate CP–OP pairs to insert shared points while avoiding potential issues from the newly created path. Experimental results on benchmarks demonstrate that SPAR can significantly reduce area overhead caused by test points while achieving almost identical or even slightly improved test coverage.

Scan structures, which are widely used in cryptographic circuits for wireless sensor networks applications, are essential for testing very-large-scale integration (VLSI) circuits. Faults in cryptographic circuits can be effectively screened out by improving testability and test coverage using a scan structure. Additionally, scan testing contributes to yield improvement by identifying fault locations. However, faults in circuits cannot be tested when a fault occurs in the scan structure. Moreover, various defects occurring early in the manufacturing process are expressed as faults of scan chains. Therefore, scan-chain diagnosis is crucial. However, it is difficult to obtain a sufficiently high diagnosis resolution and accuracy through the conventional scan-chain diagnosis. Therefore, this article proposes a novel scan-chain diagnosis method using regression and fan-in and fan-out filters that require shorter training and diagnosis times than existing scan-chain diagnoses do. The fan-in and fan-out filters, generated using a circuit logic structure, can highlight important features and remove unnecessary features from raw failure vectors, thereby converting the raw failure vectors to fan-in and fan-out vectors without compromising the diagnosis accuracy. Experimental results confirm that the proposed scan-chain-diagnosis method can efficiently provide higher resolutions and accuracies with shorter training and diagnosis times.