This paper reports a 60-GHz four-element beam-tapering phased-array transmitter with a lower sidelobe level (SLL). The array factor and the error vector magnitude (EVM) were calculated to explain the low sidelobe characteristic of a nonuniform amplitude array and to emphasize the importance of phase compensation, respectively. The phase-compensated radio frequency (RF) variable gain amplifiers (VGAs) were proposed to compensate the gain variance of phase shifters and, simultaneously, excite the nonuniform amplitude to each array element. The proposed VGA improves the relative phase error by 2° and the OP1dB by 2.4 dB within a gain control range of 5 dB, compared to the current steering without any compensation. Implemented in a commercial 65-nm CMOS process, the integrated array chip displays an root-mean-square (rms) gain error of <0.53 dB and an rms phase error of <8.8° in the frequency range of 57–66 GHz, while consuming a dc power of 403.2 mW and occupying a chip area of 2.88 mm ² . The fabricated array was integrated with a $1 \times 4$ Teflon array antenna to verify the beamforming and beam-tapering operations. With proper gain and phase control, the integrated array decreases the SLL by up to 5.2 dB, and the minimum SLL is −15.2 dB. To the best of the authors’ knowledge, this is the first report on the implementation of CMOS beam-tapering arrays in the 60-GHz band.

This letter presents a low-loss compact 60-GHz power divider/combiner (PD/C) for phased array systems. It is based on the Wilkinson power divider and employs coupled inductors with a shunt capacitor for low insertion loss and compact design. The power divider with a coupled inductor reduces the insertion loss by 0.4 dB at 60 GHz. The insertion loss is less than 0.7 dB, and the return loss is better than 10 dB over a range of 50–67 GHz. The measured isolation of the fabricated PD/C is up to 28 dB at 67 GHz. The fabricated PD/C has a compact core size of 0.0012 mm ² . To the best of our knowledge, this power divider achieves the lowest insertion loss and the smallest core area of all published 60-GHz Wilkinson PDs/Cs.

In this study, we examined a 120-GHz wideband I/Q receiver based on a baseband equalizing amplifier using 40-nm complementary metal oxide semiconductor (CMOS) technology. For low-power operation, the receiver chipset is integrated based on the direct conversion structure. To achieve high data-rate wireless communication, the receiver utilizes a frequency equalizing technique between the low noise amplifier (LNA)-mixer and baseband amplifier. With the proposed technique, the estimated overall bandwidth is increased as wider as 5 GHz. The 3-dB conversion gain bandwidth is 26 GHz, noise figure (NF) is 10.8 dB, and dc power consumption is 153.4 mW. For the dual-mode operation, the variable gain of the baseband amplifier is applied, and the conversion gain of the proposed receiver is 28.2 dB for the high gain mode and 14.8 dB for the low gain mode. The chip area of the receiver is 1.5 mm². The proposed receiver exhibits a maximum data-rate of 12.5, 16, and 16 Gb/s for binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), and 16-quadrature amplitude modulation (16-QAM), respectively.

This letter proposes a new concept of a compact multidirection-beam antenna-in-package (AiP) for mobile devices. The AiP is the first integration of three vertically polarized millimeter-wave endfire horn antennas and a broadside horn antenna on a single substrate to cover four directions. The antennas are able to connect to radio frequency integrated circuits (RFICs) situated in the cavity at the backside of the substrate using bond wires. The size of the fabricated AiP is 6 mm × 6 mm × 1.5 mm (=1.2 λ ₀ × 1.2 λ ₀ × 0.3 λ ₀ ) including 0.3 mm thickness of RFICs. The impedance bandwidth ( $| {{S_{11}}} | < - \text{15 dB}$ ) fully covers the 60 GHz band (57–66 GHz). The measured boresight gain of the endfire antenna and the broadside antenna is 5 dBi at 57 GHz and 6.3 dBi at 60 GHz, respectively.

This brief presents the design of a 60 GHz passive vector-sum phase shifter with 7-bit phase resolution. An analog X-type attenuator with complementary voltage control was used for vector modulation. The proposed attenuator is suitable for high-resolution phase shifter design because it is capable of phase inversion and shows a large attenuation range with low-phase variation. The prototype phase shifter fabricated through the 65 nm CMOS process occupies an area of 0.24 mm ² (excluding the bonding pads). The measurement results show that the proposed phase shifter achieves a phase resolution of 2.815° while exhibiting an average insertion loss of 14 dB without DC power consumption. The calculated RMS gain and phase error were below 0.55 dB and 0.83–2.36°, respectively, in the range of 57–67 GHz.