This paper reports a 60-GHz four-element beam-tapering phased-array transmitter with a lower sidelobe level (SLL). The array factor and the error vector magnitude (EVM) were calculated to explain the low sidelobe characteristic of a nonuniform amplitude array and to emphasize the importance of phase compensation, respectively. The phase-compensated radio frequency (RF) variable gain amplifiers (VGAs) were proposed to compensate the gain variance of phase shifters and, simultaneously, excite the nonuniform amplitude to each array element. The proposed VGA improves the relative phase error by 2° and the OP1dB by 2.4 dB within a gain control range of 5 dB, compared to the current steering without any compensation. Implemented in a commercial 65-nm CMOS process, the integrated array chip displays an root-mean-square (rms) gain error of <0.53 dB and an rms phase error of <8.8° in the frequency range of 57–66 GHz, while consuming a dc power of 403.2 mW and occupying a chip area of 2.88 mm ² . The fabricated array was integrated with a $1 \times 4$ Teflon array antenna to verify the beamforming and beam-tapering operations. With proper gain and phase control, the integrated array decreases the SLL by up to 5.2 dB, and the minimum SLL is −15.2 dB. To the best of the authors’ knowledge, this is the first report on the implementation of CMOS beam-tapering arrays in the 60-GHz band.

This study presents the design and analysis of a 60-GHz low-power active vector-sum phase shifter with 5-bit phase resolution. An impedance-invariant variable gain amplifier (VGA) is proposed and applied to the vector modulator. The proposed VGA not only demonstrates low phase and impedance variations during gain control but also high linearity under low supply voltage. Moreover, it reduces the gain/phase error in vector modulation. In addition, the transformer-based current-reuse technique is adopted to enhance the gain of the phased array channel while consuming low dc power. The prototype circuit implemented in 65-nm CMOS technology consumes only 5 mW of dc power and occupies an area of 0.3 mm² (excluding pads). The measurement results of the prototype circuit reveal that the proposed phase shifter achieves an average gain of -3.8 dB (including a 2-dB loss of the measurement balun), an rms gain error of 0.25-0.72 dB, and an rms phase error of 3°-7° in the 3-dB bandwidth from 51 to 66.3 GHz. The measured input 1-dB compression point is observed to be higher than -1.1 dBm at 60 GHz.

This article presents a high data rate, high-efficiency 60-GHz on-off keying (OOK) CMOS transmitter and receiver. The transmitter consists of a voltage-controlled oscillator (VCO) and a modulator. The receiver consists of a low-noise amplifier, detector, and limiting amplifier (LA) and has a compact design. An analysis of the on-off isolation of the modulator and bandwidth of the LA reveals that the proposed transformer (TF) between the modulator and the VCO can improve the on-off isolation, and the feedforward capacitor can enhance the bandwidth. Implemented in the 65-nm CMOS technology, the transmitter and the receiver consume dc powers of 12.1 and 21 mW, respectively, at 12.5 Gb/s. Moreover, they occupy core chip areas of 0.09 and 0.06 mm², respectively. The transceiver system is constructed with on-board Yagi-Uda antennas, and it achieves 12.5 Gb/s wireless OOK data transmission for a pseudorandom binary sequence of length 2⁷-1 with a bit error rate of less than 10⁻¹². The proposed transceiver system achieves an energy efficiency of 2.65 pJ/bit.

A novel quantitative design method is proposed herein for a 120-GHz 8-stage broadband amplifier using the stagger tuning technique. The pole frequencies of the unit amplifiers are determined by the parasitic capacitors and the size of the matching inductors, and resonance peaks are formed at the pole frequency. We proposed the stagger tuning technique at two different frequencies, where an inductance of four stages is chosen to match the pole frequency at a lower frequency (fL) and an inductance of the other four stages is chosen for the upper frequency (fH). With this technique, the maximum bandwidth can be achieved with the given amplifier gain. Moreover, it was shown that the amplifier designed with stagger tuning at two different frequencies yielded the lowest noise figure in the target band because the gain was concentrated in the target band. A 120-GHz 8-stage amplifier is designed with the proposed technique and fabricated using 40-nm CMOS technology. The measured peak gain of the amplifier is 20.6 dB, and the 3-dB bandwidth is 40.6 GHz while consuming 45-mW of dc power.

This letter presents a low-loss compact 60-GHz power divider/combiner (PD/C) for phased array systems. It is based on the Wilkinson power divider and employs coupled inductors with a shunt capacitor for low insertion loss and compact design. The power divider with a coupled inductor reduces the insertion loss by 0.4 dB at 60 GHz. The insertion loss is less than 0.7 dB, and the return loss is better than 10 dB over a range of 50–67 GHz. The measured isolation of the fabricated PD/C is up to 28 dB at 67 GHz. The fabricated PD/C has a compact core size of 0.0012 mm ² . To the best of our knowledge, this power divider achieves the lowest insertion loss and the smallest core area of all published 60-GHz Wilkinson PDs/Cs.

This paper presents a 60-GHz low-loss compact 4-b phase shifter in a 65-nm CMOS. It is based on a 1-b high-pass/low-pass structure and a 3-b switched-filter structure, and employs fully custom-designed capacitors with a high quality factor for low insertion loss. The phase shifter with custom-designed capacitors reduces an insertion loss by 2.6 dB at 60 GHz. The average insertion loss is 8.1 dB at 60 GHz, and the return loss is better than 10.6 dB over a range of 57-66 GHz. The measured 16-output state of the fabricated phase shifter has a phase resolution of 22.5° with an rms phase error less than 5.5° over the 57-66 GHz range. The fabricated phase shifter has a compact core size of 0.42 mm × 0.22 mm. To the best of our knowledge, this phase shifter achieves the lowest insertion loss and the smallest core area of all the published 60-GHz 360° -coverage passive CMOS phase shifters.