Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the previous latches); however, the FERST latch consumes about 50% less energy and occupies 42% less area than the triple modular redundancy (TMR) latch. Furthermore, the results show that more than 90% of the injected SETs can be masked by the FERST latch if the delay size is properly selected.

A large amount of energy in nodes of a Wireless Sensor Network (WSN) is consumed due to the inner-network communications. In this paper, an energy efficient routing algorithm is proposed which saves a significant portion of inner-network communications energy. To do this, the proposed routing algorithm selects sensor nodes with higher residual energy, more neighbors, and lower distance from the Base Station (BS) as Cluster Head (CH) nodes. Then, it manages sensor nodes appropriately and constructs clusters such a way to maximize WSN lifetime and minimize average energy dissipation per each sensor node. To evaluate the proposed routing algorithm, various simulations have been carried out by using of MATLAB simulator. The proposed routing algorithm is compared to the previous proposed algorithms e.g., LEACH, DBS, and LEACH-C algorithms. Results of the simulations show that the proposed routing algorithm has been improved the WSN performance at least 65%, reduces the energy consumption of the WSN up to 62%, and improves the successfully delivered packet ratio by at least 56% as compared to the previous routing algorithms.

The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event upsets (SEU) caused by the impact of particle strikes on system flip flops. This paper presents a novel SEU-tolerant latch where redundant feedback lines are used to mask the effects of SEUs. The power dissipation, area, reliability, and propagation delay of the presented SEU-tolerant latch are analyzed by SPICE simulations. The results show that this latch consumes about 50% less power and occupies 42% less area than a TMR-latch. However, the reliability and the propagation delay of the proposed latch are still the same as the TMR-latch. the reliability of the proposed latch is also compared with other SEU-tolerant latches.

Network-on-Chips (NoCs) have been widely used as a scalable communication solution in the design of multiprocessor system-on-chips (MPSoCs). NoCs manage communications between on-chip Intellectual Property (IP) cores and allow processing cores to achieve higher performance by outsourcing their communication tasks. NoC paradigm is based on the idea of resource sharing where hardware resources, including buffers, communication links, routers, etc., are shared between all IPs of the MPSoC. In fact, the data being routed by each NoC router might not be related to the router’s local core. Such a utilization-centric design approach can raise security issues in MPSoCs-based designs, e.g., integrity and confidentiality of the data being routed in an NoC might be compromised by unauthorized accesses/modifications of intermediate routers. Many papers in the literature have discovered and addressed security holes of NoCs, aiming at improving the security of the NoC paradigm. However, to the best of our knowledge, there is no solid survey study on the security vulnerabilities and countermeasures for NoCs. This paper will review security threats and countermeasures proposed so far for wired NoCs, wireless NoCs, and 3D NoCs. The paper aims at giving the readers an insight into the attacks and weaknesses/strengths of countermeasures.

STT-RAM technology has recently emerged as one of the most promising memory technologies. However, its major problems, limited write endurance and high write energy, are still preventing it from being used as a drop-in replacement of SRAM cache. In this paper, we propose a novel coding scheme for STT-RAM last level cache based on the concept of value locality. We reduce switching probability in cache by swapping common patterns with limited weight codes (LWC) to make writes less often as well as more uniform. We also define some policies for swapping these patterns. Our evaluation shows that bit write variance in memory cells can be reduced by about 20% on average resulting in a more uniform wear-out directly enhancing lifetime and improving cell reliability. In addition, writes in cache lines can be reduced by about 12% compared to one of the most effective circuit level techniques known as early write termination (EWT) [12]. Our method increases memory hierarchy access time by about 0.08% on average, which is negligible. We have shown that our method doesn't adversely affect last level cache energy-delay². The non-uniformity caused by the coding scheme can be used for another coding scheme at main memory or L1 cache depending on their technologies.

Approximate computing (AC) is a recently-emerged computing paradigm that can trade in accuracy for power, area, and delay in accuracy-insensitive applications such as image processing. Magnetic tunnel junction (MTJ) cells can further these AC advancements as a result of their near-zero current leakage. Additionally, due to the non-volatility of MTJs, an MTJ-based circuit can switch into a completely OFF state during idle cycles for further power savings without loss of data or the need for extra components. In this paper, two novel MTJ-based approximate full-adder circuits are proposed and evaluated. The proposed 1-bit adder circuits are then extended to an 8-bit accuracy-adaptive adder that dynamically adjusts the level of accuracy as needed. For evaluations, we have employed the proposed accuracy-adaptive adder in the implementation of a Gaussian image processing filter. We have observed that, at the expense of a tolerable loss of accuracy, the proposed accuracy-adaptive adder offers up to 47% and 94% improvements in power and performance, respectively, when compared to its conventional accurate counterparts.