Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the previous latches); however, the FERST latch consumes about 50% less energy and occupies 42% less area than the triple modular redundancy (TMR) latch. Furthermore, the results show that more than 90% of the injected SETs can be masked by the FERST latch if the delay size is properly selected.

As technology size scales down toward lower two-digit nanometer dimensions, sensitivity of CMOS circuits to radiation effects increases. Static random access memory cells (SRAMs) that are mostly employed as high-performance and high-density memory cells are prone to radiation-induced single-event upsets. Therefore, designing reliable SRAM cells has always been a serious challenge. In this paper, we propose two novel SRAM cells, namely, RHD11 and RHD13, that provide more attractive features than their latest proposed counterparts. Simulation results show that our proposed SRAM cells as compared with some state-of-the-art designs have considerably higher robustness against single-event multiple effects. Moreover, they offer a sensible area overhead advantage so that our proposed RHD11 SRAM cell has 19.9% smaller area than the prominent dual-interlocked cell. The simulation results and analyses show that our proposed SRAM cells, particularly the proposed RHD13, have a considerable lower failure probability among the considered recent radiation-hardened SRAM cells.

A large amount of energy in nodes of a Wireless Sensor Network (WSN) is consumed due to the inner-network communications. In this paper, an energy efficient routing algorithm is proposed which saves a significant portion of inner-network communications energy. To do this, the proposed routing algorithm selects sensor nodes with higher residual energy, more neighbors, and lower distance from the Base Station (BS) as Cluster Head (CH) nodes. Then, it manages sensor nodes appropriately and constructs clusters such a way to maximize WSN lifetime and minimize average energy dissipation per each sensor node. To evaluate the proposed routing algorithm, various simulations have been carried out by using of MATLAB simulator. The proposed routing algorithm is compared to the previous proposed algorithms e.g., LEACH, DBS, and LEACH-C algorithms. Results of the simulations show that the proposed routing algorithm has been improved the WSN performance at least 65%, reduces the energy consumption of the WSN up to 62%, and improves the successfully delivered packet ratio by at least 56% as compared to the previous routing algorithms.

The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event upsets (SEU) caused by the impact of particle strikes on system flip flops. This paper presents a novel SEU-tolerant latch where redundant feedback lines are used to mask the effects of SEUs. The power dissipation, area, reliability, and propagation delay of the presented SEU-tolerant latch are analyzed by SPICE simulations. The results show that this latch consumes about 50% less power and occupies 42% less area than a TMR-latch. However, the reliability and the propagation delay of the proposed latch are still the same as the TMR-latch. the reliability of the proposed latch is also compared with other SEU-tolerant latches.

In this paper, we present a very fast and accurate technique to estimate the soft error rate of digital circuits in the presence of Multiple Event Transients (METs). In the proposed technique, called Multiple Event Probability Propagation (MEPP), a four-value logic and probability set are used to accurately propagate the effects of multiple erroneous values (transients) due to METs to the outputs and obtain soft error rate. MEPP considers a unified treatment of all three masking mechanisms i.e., logical, electrical, and timing, while propagating the transient glitches. Experimental results through comparisons with statistical fault injection confirm accuracy (only 2.5% difference) and speed-up (10,000X faster) of MEPP.