The balance between computational performance and power consumption is a key constraint in computing systems, with integrated circuit technology posing a bottleneck. Approximate computation can trade off accuracy for performance or power improvement in error-tolerant scenarios. Division, with high computational demands and latency, is a bottleneck for computational efficiency. We propose a quadratic interpolation approximate divider (QIAD) based on multiplicative division, which has superior statistical performance. The design is simulated and synthesized at TSMC 65nm process and tested on image color quantization, showing the best quantization effect using evaluation indicators such as PSNR, MSE, and SSIM.

In the field of integrated circuits, the computational cost has always been a crucial design metric. In recent years, with the continuous development in the field of computing, the requirements for computation have been growing rapidly. Reducing the computational cost and improving computational efficiency have become the key issues in the field. There are many error-tolerant applications in the multimedia field where approximate computing techniques can be applied to improve computational efficiency and reduce computational costs at the cost of acceptable computational errors. This paper proposed a piecewise linear Mitchell algorithm based on Mitchell logarithmic approximation multiplication algorithm. Additionally, the Pwl-Mit multiplier is designed according to the improved algorithm combined with the data truncation technique. The proposed approximate multiplier has better statistical performance compared with the state-of-the-art multipliers. The design is simulated and synthesized at the TSMC 65 nm process, and its reliability is verified using discrete cosine transform (DCT) transform.

Artificial intelligence has revolutionized image and speech recognition, but the neural network fitting method has limitations. Neuromorphic chips that mimic biological neurons can better simulate the brain’s information processing mechanism. As the basic computing component of the new neuromorphic network, the new neural computing unit’s design and implementation have important significance; however, complex dynamical features come with a high computational cost: approximate computing has unique advantages, in terms of optimizing the computational cost of neural networks, which can solve this problem. This paper proposes a hardware implementation of an approximate spiking neuron structure, based on a simplified piecewise linear model (SPWL), to optimize power consumption and area. The proposed structure can achieve five major neuron spiking generation patterns. The proposed design was synthesized and compared to similar designs, to evaluate its potential advantages and limitations. The results showed that the approximate spiking neuron had the lowest computational cost and the fastest computation speed. A typical spiking neural network was constructed, to test the usability of the SPWL model. The results showed that the proposed approximate spiking neuron could work normally in the spiking neural network, and achieved an accuracy of 94% on the MNIST dataset.