In this work, we propose and encourage the sending of an IoT-based domestic systems conditions small scale programmable framework for grid-tie matrix converter that can efficiently be executed with low-control equipment plan with quick execution capacity. The proposed framework for matrix grid-tie converter has been performed based on an adaptive fuzzy sliding technique and furthermore monitors the grid status through an IoT server. The adaptive fuzzy sliding method was connected to the framework, and a unity power factor was fulfilled alongside the wanted sinusoidal input and output results. The proposed AFS-based matrix converter has been validated through simulation using MATLAB software. The control clock signals are generated for the positive and negative clock pulses of the sequence. Here the sinusoidal reference signal is compared with the switching frequency of the triangular carrier frequency. The hardware results were also verified to validate the simulation. When diverged from other standard techniques, the proposed AFS technique has achieved 97.23% efficiency in full load conditions.

In the present scheme of the world, the problem of shortage of power is seen across the world which can be a vulnerability to various communication securities. The scope of proposed research is that it is a step towards completing green communication technology concepts. In order to improve energy efficiency in communication networks, we designed UART using different nanometers of FPGA, which consumes the least amount of energy. This shortage is happening because of expanding of industries across the world and the rapid growth of the population. Therefore, to save the power for our upcoming generation, the globe is moving towards the concept and ideas of green communication and power‐/energy‐efficient gadget. In this work, a power‐efficient universal asynchronous receiver transmitter (UART) is implemented on 28 nm Artix‐7 field‐programmable gate array (FPGA). The objective of this work is to reduce the power utilization of UART with the FPGA device in industries. To do this, the same authors have used voltage scaling techniques and compared the results with the existing FPGA works.

With the rapidly increasing demands of e-government systems in smart cities, a myriad of challenges and issues are required to be addressed. Among them, security is one of the prime concerns. To this end, we analyze different e-government systems and find that an e-government system built with container-based technology is endowed with many features. In addition, overhauling the architecture of container-technology-driven e-government systems, we observe that securing an e-government system demands quantifying security issues (vulnerabilities, threats, attacks, and risks) and the related countermeasures. Notably, we find that the Attack Tree and Attack–Defense Tree methods are state-of-the-art approaches in these aspects. Consequently, in this paper, we work on quantifying the security attributes, measures, and metrics of an e-government system using Attack Trees and Attack–Defense Trees—in this context, we build a working prototype of an e-government system aligned with the United Kingdom (UK) government portal, which is in line with our research scope. In particular, we propose a novel measure to quantify the probability of attack success using a risk matrix and normal distribution. The probabilistic analysis distinguishes the attack and defense levels more intuitively in e-government systems. Moreover, it infers the importance of enhancing security in e-government systems. In particular, the analysis shows that an e-government system is fairly unsafe with a $99\%$ probability of being subject to attacks, and even with a defense mechanism, the probability of attack lies around $97\%$, which directs us to pay close attention to e-government security. In sum, our implications can serve as a benchmark for evaluation for governments to determine the next steps in consolidating e-government system security.

These works describe the implementation of a control unit which is an important part of Central Processing Unit (CPU) with the Field Programmable Gate Array (FPGA). In this work a frequency scaled and thermal aware energy-efficient control unit is designed with the help of 28 nanometer (nm) technology based FPGA. Frequency varies from 100MHz to 5GHz and the rise in frequency also gives rise in power consumption of control unit with FPGA. The thermal properties of FPGA also increase with increment in frequency. This whole experiment is done on Xilinx 14.1 ISE Design Suit and it is observed that lower the frequency, lower will be the power consumption of FPGA.