With the increasing demand for renewable energy power generation systems, high-power DC transmission technology is drawing considerable attention. As a result, stability issues associated with high power DC transmission have been highlighted. One of these problems is the fault current that appears when a fault occurs in the transmission line. If the fault current flows in the transmission line, it has a serious adverse effect on the rectifier stage, inverter stage and transmission line load. This makes the transmission technology less reliable and can lead to secondary problems such as fire. Therefore, fault current must be managed safely. DC circuit breaker technology has been proposed to solve this problem. However, conventional technologies generally do not take into account the effects of fault current on the transmission line, and their efficiency is relatively low. The purpose of this study is to introduce an improved DC circuit breaker that uses a blocking inductor to minimize the effect of fault current on the transmission line. It also uses a ground inductor to efficiently manage the LC resonant current and dissipate residual current. DC circuit breakers minimize adverse effects on external elements and transmission lines because the use of elements placed on each is distinct. All of these processes are precisely verified by conducting simulation under 200 MVA (±100 kV) conditions based on the VSC-based HVDC transmission link. In addition, the mechanism was explained by analyzing the simulation results to increase the reliability of the circuit in this paper.

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited four times lower I_off than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing I_on reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved drain-induced barrier lowering (DIBL) and I_off characteristics as gate channel length decreased.

In this paper, we propose a new buried channel array transistor structure to solve the problem of current leakage occurring in the capacitors of dynamic random-access memory (DRAM) cells. This structure has a superior off current performance compared with three previous types of structures. In particular, the proposed buried channel array transistor has a 43% lower off current than the conventional asymmetric doping structure. Here, we show the range of the effective buried insulator parameter according to the depth of the buried gate, and we effectively show the range of improvement for the off current.

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited 4 times lower Ioff than modified S-FinFET called RFinFET with more improved DIBL characteristics while minimizing Ion reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved DIBL and Ioff characteristics as gate channel length decreased.