In this article, we propose an analysis of the usage of a partial isolation type buried channel array transistor (Pi-BCAT). Compared with other structures, the conventional BCAT exhibits improved characteristics in the row hammer effect (RHE) because of its shallow drain/body (D/B) junction. Nevertheless, it remains affected by the RHE and should be mitigated because it is directly related to the reliability of dynamic random access memory (DRAM) applications. The proposed device exhibits a 50% improvement in the RHE and reduces leakage current ( $\textit{I}_{\biosub{off}})$ to one-third the level of conventional BCATs while also minimizing the on-current ( $\textit{I}_{\biosub{on}})$ reduction. Moreover, to efficiently compare RHE, we compare $\Delta \textit{V}_{\text{SN}}$ by RHE and $\Delta \textit{V}_{\text{SN}}$ based on the gate-induced drain leakage (GIDL) according to bias conditions and the device’s parameters. Finally, we optimize the parameter values of the buried insulator by considering electrical characteristics and the RHE.

Background: Atrial fibrillation (AF) is a well-known risk factor for stroke. Predicting the risk is important to prevent the first and secondary attacks of cerebrovascular diseases by determining early treatment. This study aimed to predict the ischemic stroke in AF patients based on the massive and complex Korean National Health Insurance (KNHIS) data through a machine learning approach. Methods: We extracted 65-dimensional features, including demographics, health examination, and medical history information, of 754,949 patients with AF from KNHIS. Logistic regression was used to determine whether the extracted features had a statistically significant association with ischemic stroke occurrence. Then, we constructed the ischemic stroke prediction model using an attention-based deep neural network. The extracted features were used as input, and the occurrence of ischemic stroke after the diagnosis of AF was the output used to train the model. Results: We found 48 features significantly associated with ischemic stroke occurrence through regression analysis (p-value < 0.001). When the proposed deep learning model was applied to 150,989 AF patients, it was confirmed that the occurrence ischemic stroke was predicted to be higher AUROC (AUROC = 0.727 ± 0.003) compared to CHA2DS2-VASc score (AUROC = 0.651 ± 0.007) and other machine learning methods. Conclusions: As part of preventive medicine, this study could help AF patients prepare for ischemic stroke prevention based on predicted stoke associated features and risk scores.

With the increasing demand for renewable energy power generation systems, high-power DC transmission technology is drawing considerable attention. As a result, stability issues associated with high power DC transmission have been highlighted. One of these problems is the fault current that appears when a fault occurs in the transmission line. If the fault current flows in the transmission line, it has a serious adverse effect on the rectifier stage, inverter stage and transmission line load. This makes the transmission technology less reliable and can lead to secondary problems such as fire. Therefore, fault current must be managed safely. DC circuit breaker technology has been proposed to solve this problem. However, conventional technologies generally do not take into account the effects of fault current on the transmission line, and their efficiency is relatively low. The purpose of this study is to introduce an improved DC circuit breaker that uses a blocking inductor to minimize the effect of fault current on the transmission line. It also uses a ground inductor to efficiently manage the LC resonant current and dissipate residual current. DC circuit breakers minimize adverse effects on external elements and transmission lines because the use of elements placed on each is distinct. All of these processes are precisely verified by conducting simulation under 200 MVA (±100 kV) conditions based on the VSC-based HVDC transmission link. In addition, the mechanism was explained by analyzing the simulation results to increase the reliability of the circuit in this paper.

As dynamic random access memory (DRAM) technologies continue to be downscaled, the partial isolation type buried channel array transistor (Pi-BCAT) structure has emerged as an innovative solution for the increasing challenges caused by leakage current adjacent to passing word lines (PWLs). This study reveals that the Pi-BCAT reduces leakage currents by 30% when compared to conventional BCAT structures. Our comprehensive simulations demonstrate that Pi-BCAT is resistant to temperature-induced leakage variations, confirming its significance in promoting consistent device performance and power management. The Pi-BCAT structure is predicted to be crucial in the advancement of DRAM reliability and efficiency, hence initiating further advancements in semiconductor technology.

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited four times lower I_off than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing I_on reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved drain-induced barrier lowering (DIBL) and I_off characteristics as gate channel length decreased.

In this paper, we compare conventional saddle type FinFETs to partial isolation type saddle FinFETs (Pi-FinFETs) using 3D TCAD simulations to examine the effect of single charge traps for proper prediction of leakage current. We simulated single charge traps at various locations in the drain region, and analyzed how the traps affect leakage current. Our results show that Pi-FinFETs enhanced the leakage current characteristics given the presence of a single charge trap. Also, it was found that Pi-FinFETs exhibit half the $\text{F}_{\mathrm {TAT}}$ of S-FinFETs. Based on the results from our analysis method, where we use $\text{I}_{\mathrm {off}}$ fluctuation, the $\text{F}_{\mathrm {TAT}}$ , the $\sigma _{\mathrm {F}}$ and the $\text{P}_{\mathrm {F}}$ parameters to accurately compare performance, and present device design guidelines aimed at improving DRAM refresh characteristics.