Motion Estimation is an essential process in many video coding standards like MPEG-2, H.264/AVC and HEVC. Despite Motion Estimation has been used at the encoder, it is expected to be used in future consumer devices in the distributed video coding architectures. But the Motion Estimation itself consumes more than 50% coding complexity or time to encode. To reduce the computation time, many fast Motion Estimation Algorithms were proposed and implemented. The present paper proposes a new fast ME algorithm which outperforms the fast ME algorithm implemented in HEVC reference software HM.

HEVC is the latest video coding standard aimed to compress double to that of its predecessor standard H.264/AVC at the cost of increased coding complexity. Motion Estimation (ME) is one of its critical tools in the encoder whose complexity drastically increases due to the increase in coding block size to 64×64 and due to the introduction of Asymmetric Motion Partitioning (AMP). Hence it requires specific hardware architectures for real time implementation. The bottleneck of ME tool is the SAD (Sum of Absolute Difference) circuit architecture which calculates SAD between current block and reference block pixels. The present paper proposes and implements three SAD architectures in FPGA. Synthesis results show that one of the proposed architectures outperforms when compared to results of other contributions, despite supporting all block modes of HEVC.

Motion estimation (ME) is one of the critical and most time consuming tasks in video coding. The increase of block size to 64x64 and introduction of asymmetric motion partitioning (AMP) in HEVC makes variable block size motion estimation more complex and therefore requires specific hardware architecture for real time implementation. The ME process includes the calculation of SAD (Sum of Absolute Difference) of two blocks, the current and the reference blocks. The present paper proposes low complexity SAD (Sum of Absolute Difference) architecture for ME of HEVC video encoder, which is able to exploit and optimize parallelism at various levels. The proposed architecture was implemented in FPGA, and compared with other non-parallel SAD architectures. Synthesis results show that the proposed architecture takes fewer resources in FPGA when compared with results from non-parallel architectures and other contributions.

We present a method which enables exact solutions to be found for flat homogeneous and isotropic scalar-tensor cosmologies with an arbitrary $\omega \left(\Phi \right)$ function, and satisfying the general perfect fluid state equation $P=\left(\gamma -1\right)\rho c^2.$ This method has been used to analyze a wide range of asymptotic analytical solutions at early and late times for different epochs in cosmic history: false vacuum inflationary models, vacuum and radiation-dominated models, and matter-dominated models. We also describe the qualitative behavior of models at intermediary times and give exact solutions at any time for some particular scalar-tensor theories.