Computing-In-memory (CIM) accelerators have the characteristics of storage and computing integration, which has the potential to break through the limit of Moore’s law and the bottleneck of Von-Neumann architecture for convolutional neural networks (CNN) implementation improvement. However, the performance of CIM accelerators is still limited by conventional CNN architectures and inefficient readouts. To increase energy-efficient performance, an optimized CNN model is required and a low-power column parallel readout is necessary for edge-computing hardware. In this work, an ReRAM-based CNN accelerator is designed. Mixed-bit operations from 1 bit to 8 bits are supported by an effective bitwidth configuration scheme to implement Neural Architecture Search (NAS)-optimized layer-wise multi-bit CNNs. Besides, column-parallel readout is achieved with excellent energy-efficient performance by a variation-reduction accumulation mechanism and low-power readout circuits. Additionally, we further explore systolic data reuse in an ReRAM-based PE array. Experiments are implemented on NAS-optimized ResNet-18. Benchmarks show that the proposed ReRAM accelerator can achieve peak energy efficiency of 2490.32 TOPS/W for 1-bit operation and average energy efficiency of 479.37 TOPS/W for 1~8-bit operations with evaluating NAS-optimized multi-bitwidth CNNs. When compared with the state-of-the-art works, the proposed accelerator shows at least 14.18× improvement on energy efficiency.

Extracting behavioral models of RRAM devices is challenging due to their unique “memory” behaviors and rapid developments, for which well-established modeling frameworks and systematic parameter extraction processes are not available. In this work, we propose a physics-informed recurrent neural network (PiRNN) methodology to generate behavioral models of RRAM devices from practical measurement/simulation data. The proposed framework can faithfully capture the evolution of internal state and its impacts on the output. A series of modifications informed by the RRAM device physics are proposed to enhance the modeling capabilities. The integration strategy of Verilog-A equivalent circuits, is also developed for compatibility with existing general-purpose circuit simulators. The Verilog-A model can be easily adopted into the SPICE-type simulator for the circuit design with a variable step that differs from the training process. Numerical experiments with real RRAM devices data demonstrate the feasibility and advantages of the proposed methodology.

The electromigration (EM)-induced reliability issues in very large-scale integration (VLSI) circuits have attracted increased attention due to the continuous technology scaling. Traditional EM models often lead to overly pessimistic predictions incompatible with the shrinking design margin in future technology nodes. Motivated by the latest success of neural networks in solving differential equations in physical problems, we propose a novel mesh-free model to compute EM-induced stress evolution in VLSI circuits. The model utilizes a specifically crafted space–time physics-informed neural network (STPINN) as the solver for EM analysis. By coupling the physics-based EM analysis with dynamic temperature incorporating Joule heating and via effect, we can observe stress evolution along multisegment interconnect trees under constant, time-dependent, and space–time-dependent temperature during the void nucleation phase. The proposed STPINN method obviates the time discretization and meshing required in conventional numerical stress evolution analysis and offers significant computational savings. Numerical comparison with competing schemes demonstrates a $2\times $ – $52\times $ speedup with a satisfactory accuracy.

Electromigration (EM) is one of the major concerns in the reliability analysis of very large-scale integration (VLSI) systems due to the continuous technology scaling. Accurately predicting the time-to-failure of integrated circuits (ICs) becomes increasingly important for modern IC design. However, traditional methods are often not sufficiently accurate, leading to undesirable over-design especially in advanced technology nodes. In this article, we propose an approach using multilayer perceptrons (MLPs) to compute stress evolution in the interconnect trees during the void nucleation phase. The availability of a customized trial function for neural network training holds the promise of finding dynamic mesh-free stress evolution on complex interconnect trees under time-varying temperatures. Specifically, we formulate a new objective function considering the EM-induced coupled partial differential equations (PDEs), boundary conditions (BCs), and initial conditions to enforce the physics-based constraints in the spatial–temporal domain. The proposed model avoids meshing and reduces temporal iterations compared with conventional numerical approaches like finite element method. Numerical results confirm its advantages on accuracy and computational performance.

In this article, we propose an exponential-integrator-Newton–Krylov (EI-NK) method for transient simulation of large-scale nonlinear circuits. This method aims to address two long-standing problems that affect the performance and robustness of EI in handling nonlinear circuits. First is the numerical instability caused by the singularity in the differential-algebraic equation system. We provide an in-depth analysis of the problem and propose a systematic, algebraic, and sparsity preserving regularization technique to eliminate the unstable modes in the system to be solved. Next, we develop a scheme to enable the iterative Newton–Raphson solution in the EI framework for enhanced nonlinearity handling capability. With the two techniques, we wish to elevate EI’s robustness and performance and make it a competitive alternative to the existing SPICE-type simulators in practical applications.

Model order reduction (MOR) has long been a mainstream strategy to accelerate large scale transient circuit simulation. Exponential integrator (EI) based on Krylov subspace approximation methods, on the other hand, are more recently developed for a similar goal. This paper aims to examine in-depth the underlying relationship between MOR and EI that are commonly seen as two separate methods. The main finding is that EI can be viewed as a moment-matching MOR in the time-domain. Specifically, EI, under certain conditions, is equivalent to performing moment-matching MOR based on rational Krylov subspace projection at each time step with a single input vector and a selected expansion point, then advancing the reduced system one step in the time-domain. The equivalence is mathematically proved under different settings and numerically verified in the experiments. Their differences in the transient circuit analysis context are also elaborated from various perspectives. It is hoped that these new insights would benefit the future development of this classical EDA topic.