Controlling the threshold voltage (V_th) of a field-effect transistor is important for realizing robust logic circuits. Here, we report a facile approach to achieve bidirectional V_th tuning of molybdenum disulfide (MoS₂) field-effect transistors. By increasing and decreasing the amount of sulfur vacancies in the MoS₂ surface, the V_th of MoS₂ transistors can be left- and right-shifted, respectively. Transistors fabricated on perfect MoS₂ flakes are found to exhibit a two-fold enhancement in mobility and a very positive V_th (18.5 ± 7.5 V). More importantly, our elegant hydrogen treatment is able to tune the large V_th to a small value (∼0 V) without any performance degradation simply by reducing the atomic ratio of S : Mo slightly; in other words, it creates a certain amount of sulfur vacancies in the MoS₂ surface, which generate defect states in the band gap of MoS₂ that mediates conduction of a MoS₂ transistor in the subthreshold regime. First-principles calculations further indicate that the defect band's edge and width can be tuned according to the vacancy density. This work not only demonstrates for the first time the ease of tuning the V_th of MoS₂ transistors, but also offers a process technology solution that is critical for further development of MoS₂ as a mainstream electronic material.

The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µ_FE /µ_o) of 85/140 cm²/V·s is presented here. The ZnO TFT was integrated with HfO₂ RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10’s of MHz.

This letter demonstrates two-orders-of-magnitude enhancement in the performance of recently reported vertical silicon nanowire (SiNW)-based thermoelectric power generators (TEGs) by optimizing the filling material. As compared to SiO₂ in the earlier work, the new device uses polyimide as filling material, which provides low parasitic thermal conduction and also reduces the damage to the nanowire tips. Consequently, an open-circuit voltage of 27.9 mV, a short-circuit current of 67 μA (both improved by ~ 17 ×), and a maximum power output of 0.47 μW (improved by ~ 313 ×) were obtained under a temperature difference of 70 K across the experimental setup. The reported improvements bring SiNW-TEGs a step closer to be used as a miniaturized clean energy source.

This paper reviews the progress of the vertical top-down nanowire technology platform developed to explore novel device architectures and integration schemes for green electronics and clean energy applications. Under electronics domain, besides having ultimate scaling potential, the vertical wire offers (1) CMOS circuits with much smaller foot print as compared to planar transistor at the same technology node, (2) a natural platform for tunneling FETs, and (3) a route to fabricate stacked nonvolatile memory cells. Under clean energy harvesting area, vertical wires could provide (1) cost reduction in photovoltaic energy conversion through enhanced light trapping and (2) a fully CMOS compatible thermoelectric engine converting waste-heat into electricity. In addition to progress review, we discuss the challenges and future prospects with vertical nanowires platform.