Rajeshwari Pandey

Dr. Rajeshwari Pandey


Research Focus & Metrics

Academic Career Length

14Years (2013-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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29 April 2014 in ISRN Electronics
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Journal Article
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RPRajeshwari Pandey
Rajeshwari Pandey
NPNeeta Pandey
Neeta Pandey
GKGurumurthy Komanapalli
Gurumurthy Komanapalli
RARashika Anurag
Rashika Anurag
Two topologies of operational transresistance (OTRA) based third order quadrature oscillators (QO) are proposed in this paper. The proposed oscillators are designed using a combination of lossy and lossless integrators. The proposed topologies can be made fully integrated by implementing the resistors using matched transistors operating in linear region, which also facilitates electronic tuning of oscillation frequency. The nonideality analysis of the circuit is also given and for high frequency applications self-compensation can be used. Workability of the proposed QOs is verified through PSPICE simulations using 0.5 μm AGILENT CMOS process parameters. The total harmonic distortion (THD) for both the QO designs is found to be less than 1%.

17 March 2013 in ISRN Electronics
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Journal Article
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RPRajeshwari Pandey
Rajeshwari Pandey
NPNeeta Pandey
Neeta Pandey
TNTushar Negi
Tushar Negi
VGVivek Garg
Vivek Garg
Current difference buffered amplifier (CDBA) based universal inverse filter configuration is proposed. The topology can be used to synthesize inverse low-pass (ILP), inverse high-pass (IHP), inverse band-pass (IBP), inverse band-reject (IBR), and inverse all-pass filter functions with appropriate admittance choices. Workability of the proposed universal inverse filter configuration is demonstrated through PSPICE simulations for which CDBA is realized using current feedback operational amplifier (CFOA). The simulation results are found in close agreement with the theoretical results.

2 January 2020 in Journal of Information and Optimization Sciences
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Journal Article
Closed access
SASaji M. Antony
Saji M. Antony
SIS. Indu
S. Indu
RPRajeshwari Pandey
Rajeshwari Pandey
A wireless sensor network is a network of spatially deployed sensor nodes with constrained energy resources. This research paper focusses to design a robust solar energy harvesting system to enhance life time of sensor nodes. Proposed solar energy supply system mainly consists of a solar panel, rechargeable battery and a control circuit. To obtain sufficient voltage to charge battery, electrical energy generated through panel is boosted by boost converter. Different sensor nodes are supplied with energy from this system. An inverter is also designed for AC applications. Complete structure of the system, design of each module, details of implementation and evaluation of performance are explained in this work. Experimental results show that this compact, self-sufficient system enables outdoor based wireless sensor network nodes to operate successfully.

1 May 2016 in IET Circuits, Devices & Systems
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Journal Article
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NPNeeta Pandey
Neeta Pandey
DNDeva Nand
Deva Nand
RPRajeshwari Pandey
Rajeshwari Pandey
This paper proposes two generalised instrumentation amplifier topologies which can operate in voltage, current, transadmittance, and transimpedance mode. Each topology is a two stage structure, wherein an amplifier is used as first stage in the first topology and a converter is employed in the second one. The second stage is difference amplifier for both the structures. The theoretical proposition is verified through operational floating current conveyor (OFCC). The effect of non‐idealities of OFCC on system performance, in particular finite transimpedance and tracking error, is also analysed and corresponding mathematical formulation is presented. The functional verification is performed through SPICE simulation using CMOS‐based implementation of OFCC. The experimental results using current feedback operational amplifier‐based OFCC implementation are also included which are in close agreement with theoretical and simulated results.

18 July 2013 in Active and Passive Electronic Components
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Journal Article
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NPNeeta Pandey
Neeta Pandey
RPRajeshwari Pandey
Rajeshwari Pandey
This paper presents a current mode full-wave rectifier based on single modified Z copy current difference transconductance amplifier (MZC-CDTA) and two switches. The circuit is simple and is suitable for IC implementation. The functionality of the circuit is verified with SPICE simulation using 0.35 μm TSMC CMOS technology parameters.

23 December 2014 in Advances in Electronics
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Journal Article
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NPNeeta Pandey
Neeta Pandey
ASAseem Sayal
Aseem Sayal
RCRicha Choudhary
Richa Choudhary
RPRajeshwari Pandey
Rajeshwari Pandey
This paper presents frequency agile filters based on current difference transconductance amplifier (CDTA) and voltage difference transconductance amplifier (VDTA). The proposed agile filter configurations employ grounded passive components and hence are suitable for integration. Extensive SPICE simulations using 0.25 μm TSMC CMOS technology model parameters are carried out for functional verification. The proposed configurations are compared in terms of performance parameters such as power dissipation, signal to noise ratio (SNR), and maximum output noise voltage.