The effective control and management of traffic at intersections is a challenging issue in the transportation system. Various traffic signal management systems have been developed to improve the real-time traffic flow at junctions, but none of them have resulted in a smooth and continuous traffic flow for dealing with congestion at road intersections. Notwithstanding, the procedure of synchronizing traffic signals at nearby intersections is complicated due to numerous borders. In traditional systems, the direction of movement of vehicles, the variation in automobile traffic over time, accidents, the passing of emergency vehicles, and pedestrian crossings are not considered. Therefore, synchronizing the signals over the specific route cannot be addressed. This article explores the key role of real-time traffic signal control (TSC) technology in managing congestion at road junctions within smart cities. In addition, this article provides an insightful discussion on several traffic light synchronization research papers to highlight the practicability of networking of traffic signals of an area. It examines the benefits of synchronizing the traffic signals on various busy routes for the smooth flow of traffic at intersections.

The conventional six-transistor static random access memory (SRAM) cell allows high density and fast differential sensing but suffers from half-select and read-disturb issues. Although the conventional eight-transistor SRAM cell solves the read-disturb issue, it still suffers from low array efficiency due to deterioration of read bit-line (RBL) swing and Ion/Ioff ratio with increase in the number of cells per column. Previous approaches to solve these issues have been afflicted by low performance, data-dependent leakage, large area, and high energy per access. Therefore, in this paper, we present three iterations of SRAM bit cells with nMOS-only based read ports aimed to greatly reduce data-dependent read port leakage to enable 1k cells/RBL, improve read performance, and reduce area and power over conventional and 10T cell-based works. We compare the proposed work with other works by recording metrics from the simulation of a 128-kb SRAM constructed with divided-wordline-decoding architecture and a 32-bit word size. Apart from large improvements observed over conventional cells, up to 100-mV improvement in read-access performance, up to 19.8% saving in energy per access, and up to 19.5% saving in the area are also observed over other 10T cells, thereby enlarging the design and application gamut for memory designers in low-power sensors and battery-enabled devices.

This paper presents a new approach for third order quadrature oscillator (QO) realisation. It uses a high pass filter and differentiator connected in a feedback loop. A differential voltage current conveyor transconductance amplifier (DVCCTA) is employed to verify the proposed approach. Two circuit topologies of QO have been proposed. Both the topologies utilise two DVCCTA and three grounded capacitors. In addition, the first topology employs a single resistor while the second makes use of two resistors. The circuits exhibit orthogonal control on frequency and condition of oscillation. The quadrature current outputs are available at high output impedance and voltage outputs are also present. The theoretical proposition has been verified through SPICE simulations using 0.25 μm Taiwan semiconductor manufacturing company (TSMC) complementary metal oxide semiconductor (CMOS) technology parameters. Experimental results are also included which corroborate the theoretical propositions and simulated results.

Two topologies of operational transresistance (OTRA) based third order quadrature oscillators (QO) are proposed in this paper. The proposed oscillators are designed using a combination of lossy and lossless integrators. The proposed topologies can be made fully integrated by implementing the resistors using matched transistors operating in linear region, which also facilitates electronic tuning of oscillation frequency. The nonideality analysis of the circuit is also given and for high frequency applications self-compensation can be used. Workability of the proposed QOs is verified through PSPICE simulations using 0.5 μm AGILENT CMOS process parameters. The total harmonic distortion (THD) for both the QO designs is found to be less than 1%.

Subthreshold and near-threshold operations are viable approaches towards reducing both static and dynamic power in Static Random Access Memory (SRAM). However, supply scaling in SRAM cells is severely limited by process variations. Additionally, cell performance is greatly affected by local mismatch in subthreshold region, thereby prohibiting low voltage operation. In order to mitigate these issues, we present a ten-transistor (10T) SRAM cell with capability of performing a variation tolerant write operation in deep subthreshold region without the implementation of additional peripheral circuitry or assist technique. The unique topology of the proposed cell also aids in reducing the bit line offset voltage, thereby improving read access performance. In addition to read and write performance, the hold stability has also been improved, resulting in significant Vmin gains. The Vmin of all cells has been evaluated at the 6σ failure point (P _Fail = 10 ^-9 ) using a comprehensive pentavariate probability anaylsis, considering both static and dynamic measures. At respective Vmin, the proposed 10T cell consumes up to 39× and 6.6× lower hold power than the conventional 6T and 8T cells, making it a viable candidate for portable electronics or low power sensors.