Deepak Kumar

Mr. Deepak Kumar


Research Focus & Metrics

Academic Career Length

11Years (2016-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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12 April 2018 in Wireless Personal Communications
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Journal Article
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AKADESH KUMAR
ADESH KUMAR
GVGaurav Verma
Gaurav Verma
MGmukul kumar gupta
mukul kumar gupta
MSMohammad Salauddin
Mohammad Salauddin
BRBilawal Rehman
Bilawal Rehman
DKDeepak Kumar
Deepak Kumar

1 December 2021 in Engineering Research Express
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Journal Article
Closed access
DKDeepak Kumar
Deepak Kumar
Population growth significantly expanding the boundaries of residential areas and living standards for humankind results in a tremendous increase in energy consumption. Unlike fossil fuels, which are found only in a few sites and non-renewable sources, solar energy is renewable and freely available in every part of the world. A dye-sensitized solar cell (DSSC) is a suitable electrochemical device to harness solar energy to produce power and is advantageous for its simplicity and inexpensive cost. Variations in photo-electrodes micro/nanostructure shape, doping, size, and crystal phase can improve the DSSCs performance by enhancing dye loading, improved light scattering ability, and/or faster electron transit and longer electron lifetime. The high yielding techniques for producing diverse morphologies for nanoparticles with appropriate band gaps might thus be considered another feasible strategy for improving cell performance. The impact of influencing parameters on photovoltaic characteristics of photo-anode for DSSC application is investigated in this review article. The descriptions are presented by compiling a list of relevant literature reports.

1 December 2019 in Engineering Research Express
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Journal Article
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DKDeepak Kumar
Deepak Kumar
In this work, a Lookup table based verilog-A model is employed in cadence to evaluate the performance of the chain of inverters and 6-T SRAM cell based on double gate Tunnel-field-effect transistor (DGTFET). In order to drive large capacitance with fixed number of inverters stages with constant width of N type DGTFET (W n ), it is found that the time delay performance of the inverter chain depends on the ratio of width of P type DGTFET of nth stage (Wp n ) to width of P type DGTFET of n-1th stage (Wp n−1 ). Simulation results investigated that the time delay is minimized to 0.265 ns for Wp n /Wp n−1 = 3. The impact of cell ratio (CR) and pull up ratio (PR) on the read stability and write ability of 6-T SRAM cell are investigated by using N curve simulations. It is observed that, increasing CR and PR strengthens the read stability and degrades the write ability of 6-T SRAM cell.

18 September 2016
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Book Chapter
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AYAmitabh Yadav
Amitabh Yadav
VKVivek Kaundal
Vivek Kaundal
ASAbhishek Sharma
Abhishek Sharma
PSPaawan Sharma
Paawan Sharma
DKDeepak Kumar
Deepak Kumar
PBPankaj Badoni
Pankaj Badoni


30 April 2019 in Nanotechnology Perceptions
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Journal Article
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DKDeepak Kumar
Deepak Kumar
ABA Bist
A Bist
PDP Dua
P Dua
PKP Kuchhal
P Kuchhal
GAGagan Anand
Gagan Anand
KPK.P.S. Parmar
K.P.S. Parmar