Anomaly detection is becoming increasingly important to enhance reliability and resiliency in the Industry 4.0 framework. In this work, we investigate different methods for anomaly detection on in-production manufacturing machines taking into account their variability, both in operation and in wear conditions. We demonstrate how the nature of the available data, featuring any anomaly or not, is of importance for the algorithmic choice, discussing both statistical machine learning methods and control charts. We finally develop methods for automatic anomaly detection, which obtain a recall close to one on our data. Our developed methods are designed not to rely on a continuous recalibration and hand-tuning by the machine user, thereby allowing their deployment in an in-production environment robustly and efficiently.

In this article, we compare several concepts for gallium‐nitride (GaN) power high electron mobility transistor (HEMT) packages in terms of their drain‐to‐source parasitic inductance and resistance values. Unlike in previous studies, however, due to several fast transient use cases the investigated frequencies are extended to 2 GHz. Since the device's dimensions are already a significant fraction of the corresponding wavelength at 2 GHz, full wave simulation tools have been employed to more accurately assess the problem. The results reveal how the considered package concepts affect the overall parasitic device impedances and show a clear improvement of the parasitic impedance over each generation of package implementation. Furthermore, full wave analysis results are compared to method of moments results to emphasize the necessity of full wave simulations at these frequencies.

With the ongoing trend toward miniaturization via system-on-chip (SoC), both radio-frequency (RF) SoCs and on-chip multi-sensory systems are gaining significance. This paper compares the inductance of a miniaturized on-chip near field communication (NFC) antenna versus the conventional screen-printed on-substrate ones that have been used for the transfer of sensory data from a chip to a cell phone reader. Furthermore, the transferred power efficiency in a coupled NFC system is calculated for various chip coil geometries and the results are compared. The proposed NFC antenna was fabricated via a lithography process for an application-specific integrated circuit (ASIC) chip. The chip had a small area of 2.4 × 2.4 mm², therefore a miniaturized NFC antenna was designed, whereas the screen-printed on-substrate antennas had an area of 35 × 51 mm². This paper investigates the effects of different parameters such as conductor thickness and materials, double layering, and employing ferrite layers with different thicknesses on the performance of the on-chip antennas using full-wave simulations. The presence of a ferrite layer to increase the inductance of the antenna and mitigate the interactions with backplates has proven useful. The best performance was obtained via double-layering of the coils, which was similar to on-substrate antennas, while a size reduction of 99.68% was gained. Consequently, the coupling factors and maximum achievable power transmission efficiency of the on-chip antenna and on-substrate antenna were studied and compared.