Glass frit bonding is a widely used technology to cap and seal micro-electromechanical systems on the wafer level using a low melting point glass. Screen printing is the main method to apply glass frit paste on wafers. Screen printing of glass frit paste is usually performed on less sensitive, less critical wafers, normally the capping wafer, because screen printing is a rough process involving the mechanical contact of the screen printing mesh and the wafer. However, for some applications in which contactless patterning of glass frit materials on the device wafers are preferred (e.g., 3D topographies, micro-lens and optics integration) jet dispensing could be a promising approach. Consequently, in this study, wafer-level jetting of glass frit materials on silicon wafers was proposed and investigated. The jetting parameters such as jetting distance, power and temperature were optimized for a glass frit paste. Additionally, the effect of jetted pitch size on the bond-line thickness was assessed. The wafers with jetted glass frit pastes were conclusively bonded in low vacuum and characterized. As a single-step (non-contact) additive approach, the jet printing of glass frit was revealed to be a straightforward, cost-effective and flexible approach with several implications for hermetic packaging.

Copper sinter paste has been recently established as a robust die-attach material for high -power electronic packaging. This paper proposes and studies the implementation of copper sinter paste materials to create top-side interconnects, which can substitute wire bonds in power packages. Here, copper sinter paste was exploited as a fully printed interconnect and, additionally, as a copper clip-attach. The electrical and thermal performances of the copper-sinter paste interconnections (“sinterconnects”) were compared to a system with wire bonds. The results indicate comparable characteristics of the sinterconnect structures to the wire-bonded ones. Moreover, the performance of copper sinterconnects in a power module was further quantified at higher load currents via finite element analysis. It was identified that the full-area thermal and electrical contact facilitated by the planar sinterconnects can reduce ohmic losses and enhance the thermal management of the power packages.

Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, and prototyping of flexible devices. There is a high demand for thin silicon devices for several applications, such as flexible electronics. To address this demand, we study a novel post-processing method on two silicon devices, an electrochemical impedance sensor, and Complementary Metal Oxide Semiconductor (CMOS) die. Both are drawn from an MPW batch, thinned at die-level after dicing and singulation down to 60 µm. The thinned dies were flip-chip bonded to flexible substrates and hermetically sealed by two techniques: thermosonic bonding of Au stud bumps and anisotropic conductive paste (ACP) bonding. The performance of the thinned dies was assessed via functional tests and compared to the original dies. Furthermore, the long-term reliability of the flip-chip bonded thinned sensors was demonstrated to be higher than the conventional wire-bonded sensors.

With the ongoing trend toward miniaturization via system-on-chip (SoC), both radio-frequency (RF) SoCs and on-chip multi-sensory systems are gaining significance. This paper compares the inductance of a miniaturized on-chip near field communication (NFC) antenna versus the conventional screen-printed on-substrate ones that have been used for the transfer of sensory data from a chip to a cell phone reader. Furthermore, the transferred power efficiency in a coupled NFC system is calculated for various chip coil geometries and the results are compared. The proposed NFC antenna was fabricated via a lithography process for an application-specific integrated circuit (ASIC) chip. The chip had a small area of 2.4 × 2.4 mm², therefore a miniaturized NFC antenna was designed, whereas the screen-printed on-substrate antennas had an area of 35 × 51 mm². This paper investigates the effects of different parameters such as conductor thickness and materials, double layering, and employing ferrite layers with different thicknesses on the performance of the on-chip antennas using full-wave simulations. The presence of a ferrite layer to increase the inductance of the antenna and mitigate the interactions with backplates has proven useful. The best performance was obtained via double-layering of the coils, which was similar to on-substrate antennas, while a size reduction of 99.68% was gained. Consequently, the coupling factors and maximum achievable power transmission efficiency of the on-chip antenna and on-substrate antenna were studied and compared.

This paper demonstrates the feasibility of the printed copper (Cu) paste interconnects for applications in power semiconductor modules and switching converters. Copper sinter paste interconnects denoted as “Sinterconnects” have been recently introduced as an alternative to wire-bonding technology for power electronic device packaging. However, the electrical domain properties of these novel interconnects have not yet been investigated in detail. To address this research opportunity, this paper evaluates the performance of two different types of Sinterconnects applied to multi-chip, insulated gate bipolar transistor (IGBT) power modules. First, parasitic or stray inductances of these Sinterconnected systems are calculated analytically and by using three-dimensional finite element (FE) analysis. In addition to that, resistivity ($\rho$) of those has been analysed and compared with conventional wire bond technology. Finally, the performances of the Sinterconnects in power device assemblies are experimentally investigated. Two Sinterconnect structures (i.e., printed Cu paste and Cu clip attach) as well as a state-of-the-art wire-bonded IGBT module, have been integrated into a switching DC-DC converter and benchmarked. Experimental measurements show how converters with Sinterconnects enable efficient power conversion.