This study presents a new sub-10-nm tunnel field-effect transistor (TFET) with bandgap engineering using a graded Si/Ge heterojunction. Both the height and width of the tunneling barrier are highly controlled by applying gate voltages to ensure a near ideal sub-5-mV/dec switching of scaled sub-10-nm TFETs at 300 K. This study performed a 2-D simulation to elucidate p-body graded Si/Ge heterojunction TFET devices from 50 to 5 nm. The on-state tunneling barrier around the source was narrowed and lowered to demonstrate a high on-current; simultaneously, the off-state tunneling barrier was raised and extended into the drain to control the short-channel effect and ambipolar leakage current. The shorter the length is, the more abrupt is the switching. The breakthrough in subthreshold swing and short-channel effect make the graded Si/Ge TFET highly promising as an ideal green transistor into sub-10-nm regimes.

Using graded silicon-germanium heterojunctions, the green tunnel field-effect transistor (TFET) can be scaled down into sub-10 nm regimes without short-channel effects. This work elucidates numerically the physical operation and device design of extremely short-channel TFETs with graded silicon-germanium heterojunctions for future low-power and high-performance applications. Critical device factors, such as the drain profile and bandgap engineering, were examined to generate favorable characteristics in the on-current, on-off switching, and off-leakage of very short TFETs. A mildly doped drain with a pure Ge source is preferred in designing the graded TFETs to optimize a desirable green transistor for low-power integrated circuits.

The low-bandgap engineering and line-tunneling architecture are the two major techniques to resolve the ON-current issues of tunnel field-effect transistors (TFETs). This paper elucidates the design and modeling of line-tunneling TFETs using low-bandgap materials. Three semiconductors, Ge, InAs, and InSb, are considered as examples to explore their physical operations and analytical models. 2-D device simulations were performed to examine the on/off characteristics. The appropriate operational voltages depend on the associated bandgap of semiconductors. The gate voltage should be larger than the bandgap voltage (E _g /q) to ensure high ON-currents, whereas the drain voltage must be less than the bandgap voltage to control OFF-leakages. Because the minimum tunnel path has a key function in determining the tunneling in line-tunneling TFETs, the tunneling current is reformulated in terms of the minimum tunnel path with friendly compact forms. Two prime design factors, the source concentration and gate-insulator thickness, are examined both analytically and numerically, showing the minimum tunnel path can serve as a useful indicator for low-bandgap line-tunneling TFETs.

A new Schottky barrier (SB) nonvolatile nanowire memory is reported experimentally with efficient low-voltage programming and erasing. By applying an SB source/drain to enhance the electrical field in the silicon gate-all-around nanowire, the nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory can operate at gate voltages of 5 to 7 V for programming and -7 to -9 V for erasing through Fowler-Nordheim tunneling. The larger the gate voltage is, the faster the programming/erasing speed and the wider the threshold-voltage shift are attained. Importantly, the SB nanowire SONOS cells exhibit superior 100-K cycling endurance and high-temperature retention without any damages from metallic silicidation process or field-enhanced tunneling.