Vertical-cavity surface-emitting lasers (VCSELs) are commonly used in high-speed optical communication and 3D sensing applications. Both of these applications require high switching frequency and a short rise time of the VCSEL current. The parasitic inductance of the wire (connecting the driver with VCSEL) makes it challenging to achieve a short rise time, which often incur increased supply voltage and excessive power consumption. This paper utilizes a momentary boosting in supply voltage to overcome the parasitic inductance of the wire with minimal power overhead. The proposed technique uses a precalculated boosting capacitance to produce negative voltage for common-anode VCSELs. The boosting capacitance provides the required amount of charge during the rising transition and automatically disconnects itself in steady-state. Circuit simulations reveal up to three times shorter rise time at the negligible cost of less than 10% power overhead.

This paper presents a reconfigurable on-chip switched capacitor (SC) voltage converter aimed at ultra-low- power (ULP) applications. The proposed voltage converter provides an additive advantage of energy saving during both sleep-to-active and active-to-sleep transitions. This is done by incorporating two techniques, so called, split-capacitor charging (step-wise charging), and energy recycling. Split-capacitor charging is proved to reduce the energy loss during the sleep-to-active transition by 66 %. An existing symmetric energy recycling technique recovers 75 % of the energy from the capacitor bank at the expense of a large output voltage ripple. In this paper, an improved method called asymmetric energy recycling reconfiguration(s) is introduced. The asymmetric energy recycling reduces the output voltage ripple by 50 % compared to the symmetric recycling technique, without sacrificing the recycling efficiency. It can salvage 75.42 % of the capacitor energy in active-to-sleep transition, which would have been wasted through leakages during a long sleep period. Circuit simulations of the proposed SC voltage converter demonstrate up to 23.13 % improvement in energy efficiency, compared to conventional SC converters for a short active period.

Modern sensor nodes have multiple operating states, which causes a conventional voltage converter to perform poorly over a wide load range of the operating states. This paper proposes a voltage converter whose switching frequency and output voltage are proactively adjusted to maintain high conversion efficiency. This allows the converter to exploit a wider frequency range to cover a wide load range. In addition, the proposed converter uses multiple smaller capacitor banks and employs multiphase operation to provide low output ripple voltage. A distributed topology for non-overlapping signal generation is proposed and used in the converter to minimize the number of wires running from connecting the controller to the converter. The proposed voltage converter has been implemented in a chip using a 0.13 um CMOS process. The measurement results demonstrate the ability to support a wide load range of 10 µA to 10 mA, for switching frequencies ranging from 100 kHz to 200 MHz, while providing an efficiency of above 80%.

Modern internet-of-things (IoT) applications need voltage converters to efficiently supply power with a small active period at various load conditions. The energy losses in such voltage converters during transitions between sleep-active can be significant, especially when the converters deviate from their optimum load conditions. The proposed Switched Capacitor (SC) converter, fully integrated on chip, incorporates Split-Capacitor Charging (SCC) and Energy Recycling (ER) techniques to minimize the energy losses during the transitions. The converter consists of multiple capacitor banks and their size increases in a binary exponential fashion. It employs an LDO to support a wide range of output voltage levels and reduce output voltage ripple during energy recycling and Continuous phase. In addition, we introduce an efficient test circuit structure using an on-chip digital controller and reconfigurable load circuit. This test structure can eliminate the unwanted parasitic values and varying delays, which are commonly incurred in the conventional test structures of on-chip voltage converters with off-chip loads and external control signal generation. We implemented the proposed voltage converter with a complete on-chip test structure using a 0.13um CMOS process. Measurement results demonstrate a maximum efficiency of 86.83% for a load current of μA It also achieved an improvement of 64.44% in energy efficiency over conventional voltage converters for a short active period.

Convolutional Neural Networks benefit from higher accuracy at the cost of higher hardware requirements and power consumption. The multiply and accumulate unit ((MAC), which perform the convolution operation inside a CNN, consumes a significant amount of power consumption. In this work we propose a mixed-signal approach for implementing analog MAC unit that can replace the digital MAC units in CNNs. The Analog MAC unit architecture is constituted from binary weighted current steering DAC circuit and capacitors. A digital parallel interfaced is designed to provide input image and filter values to the MAC unit. To realize an input layer for the CNN a low power ADC is then employed at the output to convert the final value back to digital value. When a 3×3 convolution is performed the analog MAC unit offers area and power consumption benefits.