The design of a solar PV system and its performance evaluation is an important aspect before going for a mass-scale installation and integration with the grid. The parameter evaluation of a solar PV model helps in accurate modeling and consequently efficient designing of the system. The parameters appear in the mathematical equations of the solar PV cell. A Chaos Induced Coyote Algorithm (CICA) to obtain the parameters in a single, double, and three diode model of a mono-crystalline, polycrystalline, and a thin-film solar PV cell has been proposed in this work. The Chaos Induced Coyote Algorithm for extracting the parameters incorporates the advantages of the conventional Coyote Algorithm by employing only two control parameters, making it easier to include the unique strategy that balances the exploration and exploitation in the search space. A comparison of the Chaos Induced Coyote Algorithm with some recently proposed solar photovoltaic cell parameter extraction algorithms has been presented. Analysis shows superior curve fitting and lesser Root Mean Square Error with the Chaos Induced Coyote Algorithm compared to other algorithms in a practical solar photovoltaic cell.

Reliability of the multilevel inverters (MLIs) is one of the most important concerns in industrial applications, mainly due to the semiconductor devices. Whenever a fault occurs in one of the switches of the inverter, it leads to abnormal conditions and can also cause serious damage to the equipment connected to the multilevel inverter. In this paper, a recently proposed nine-level Packed-E-Cell (PEC) multilevel inverter topology is investigated for its fault-tolerant capability and improved reliability. The analysis is carried out for a reduced device multilevel inverter topology that, due to a lack of redundant states, cannot tolerate switch failures. The fault-tolerant (FT) topology provides additional redundant states in the switching sequence of the existing topology. The work in this paper presents Packed-E-Cell MLI modified for fault tolerance against single-switch open-circuit faults. The modified FT topology inherently achieves self-voltage balance in the DC-link capacitors. Nearest Level Control(NLC) is used as the modulation strategy for generating the desired switching pulses. Simulation results are obtained in MATLAB/Simulink for the conditions prior to the fault, during the fault and post fault, and results are discussed. Experimental verification of the modified FT topology is also performed, in order to validate its effectiveness.