This paper proposes a novel sensor-less switching method based on logic gates for a five-level packed U-cell (PUC5) converter. It comprises only two level-shifted triangular carriers and logic gates. Hence, the number of triangular carriers is halved and the switching states table is eliminated, which cause remarkable reduction in complexity of the proposed modulation method. Moreover, employing the proposed sensor-less switching method leads to decrease in the PUC5 capacitor value by a factor of carrier ratio, fast self-balancing of the PUC5 capacitor voltage, and halving the output LC filter inductor and capacitor values in stand-alone mode, as well as the grid-link inductor value in grid-connected mode. In addition, the PUC5 converter start-up transient time is considerably decreased and the first switching harmonic cluster frequency is doubled, which lead to notable improvement of steady-state and dynamic performances of the PUC5 converter. The proposed sensor-less switching method has been implemented in both stand-alone and grid-connected operating modes of PUC5 converter. Provided simulation and experimental results verify the feasibility and effectiveness of the proposed sensor-less switching method as well as its improved dynamic and steady-state performances in both stand-alone and grid-connected modes.

In this paper, a new configuration of modular multilevel converter (MLC) based on parallel connection of 3-level active-neutral-point-clamped (3L-ANPC) cells as well as its improved modulation method are proposed for 1MHz, 1MW EV mega-charger. In the proposed paralleled modular ANPC MLC, only six high frequency silicon carbide (SiC) power switches operating at 333 kHz are required to generate 1MHz switching frequency spectrum. Moreover, the operating voltage of all power devices is halved, the magnitude of the first switching frequency harmonic cluster is decreased by factor of five, and the load current is equally distributed between the 3L-ANPC legs by employing the proposed improved modulation method. Hence, the modularity, efficiency, and power density of the proposed converter are notably increased whereas the value of passive components and the overall switching loss are remarkably decreased. In addition, an optimized design of the one 3L-ANPC cell of the proposed paralleled modular ANPC MLC for 1MHz, 1MW EV mega-charger using ANSYS SIwave, Icepak, and Q3D finite element method (FEM) platforms is presented and analyzed in detail. The provided experimental results of the down-scaled setup verify the feasibility and viability of the proposed configuration as well as its improved switching pattern.

In this paper, a novel generalized circuit topology of the n-time quadrupled-hybrid-neutral-point-clamped (Qn-HNPC) converter and a new decomposed sensor-less modulation method are proposed to multiply the number of output voltage levels of the 5L-HNPC converter with a less number of components. The Qn-HNPC converter is realized by applying $n$ number of the proposed voltage-level multiplier modules (VLMMs) to the 5L-HNPC converter. Hence, the number of output voltage levels is n-time quadrupled in the attained Qn-HNPC converter, whereas a less number of components, as well as, low cost and size, are added to the main 5L-HNPC converter. Moreover, a novel generalized decomposed sensor-less modulation method is introduced to decompose the main 5L-HNPC and the proposed VLMMs reference signals in the attained Qn-HNPC converter. Consequently, only four low-voltage and low-power switches operate at switching frequency, whereas the remaining devices commutate at the low or fundamental frequency. Furthermore, employing the proposed modulation method in the attained Qn-HNPC converter causes self-balancing of all the capacitors voltage, doubling the first switching harmonic cluster frequency of the output voltage, as well as a remarkable decrease in the control complexity, the stored energy, and the size of the VLMMs capacitor. The presented simulation and experimental results verify the performance and viability of the proposed Qn-HNPC converter topology, as well as, the suggested decomposed modulation method.

In this paper, a new configuration of single DC source hybrid packed U-cell (H-PUC) converter with reduced number of components is proposed. The proposed H-PUC only requires one dc source, twelve power switches, and three capacitors to provide 23-level output voltage. It is comprised of two high voltage low frequency (LF) and low voltage high frequency (HF) sub-modules which leads to less power losses and higher efficiency of the proposed H-PUC converter. Moreover, a finite control set model predictive control (FCS-MPC) method is proposed to generate 23-level staircase output voltage with low THD and to regulate voltages of three capacitors to their desired values simultaneously. A real-time model of the proposed 23-level H-PUC converter and its suggested FCS-MPC are developed and implemented in OPAL-RT OP4510 platform to evaluate and validate the feasibility of the proposed H-PUC in grid-connected operation mode. The provided real-time implementation results verify and demonstrate the performance and viability of the proposed 23-level H-PUC and its associated FCS-MPC to provide low THD 23-level output voltage and all three capacitors voltages balancing.

This paper proposes a novel 11-level improved active-neutral-point-clamped (11L-IANPC) converter for ground power unit (GPU) application. This hybrid topology consists of the 5L-ANPC and the proposed low-voltage submodule. The proposed 11L-IANPC converter possesses only one flying capacitor (FC) and reduced number of high-frequency switches. Hence, voltage diversity and ratings, stored energy, and the number of costly and bulky FCs are significantly decreased. Moreover, operating the augmented submodule at the low voltage and power leads to doubling the number of output voltage levels, whereas the low extra cost and size are imposed on the proposed converter. In addition, suggested sensorless switching method leads to self-balancing of FC and significantly amends the output voltage frequency spectrum. These improvements cause significant reduction in control complexity of the proposed 11L-IANPC converter, remarkable decrease in size of the bulky and costly output LC filter, and improving the dynamic and steady-state performance of the proposed static GPU. The simulation and experimental results validate the feasibility of the proposed converter as well as its suggested modulation and control method.

Multilevel voltage-source converters are well-suited for power conversion applications demanding higher power density, reliability, efficiency, and power quality. An unremitting and persistent research for developing advanced multilevel converter topologies with improved characteristics, performance, modulation techniques, and control methods continues. This paper proposes duo-neutralpoint- clamped (D-NPC), duo-active-neutral-point-clamped (D-ANPC), and duo-neutral-point-piloted (D-NPP) multilevel voltage-sourced converter topologies. The D-NPC, D-ANPC, and D-NPP converters phase-leg is realized by adding low-frequency semiconductor power switches to their structures. This results in a substantial reduction in the number of the high-frequency pulse-widthmodulation (PWM) insulated-gate bipolar transistors (IGBTs) and clamping passive devices including diodes as well as flying-capacitors (FCs). Moreover, a drastic abatement in the total voltage rating and total stored energy of the FCs within the D-ANPC topology is achieved compared to the classic ANPC configuration. The experimental results are provided for D-NPC, D-ANPC, and D-NPP converters to validate the feasibility of their topology and modulation method for control of the multilevel Multilevel voltage-source converters are well-suited for power conversion applications demanding higher power density, reliability, efficiency, and power quality. An unremitting and persistent research for developing advanced multilevel converter topologies with improved characteristics, performance, modulation techniques, and control methods continues. This paper proposes duo-neutralpoint- clamped (D-NPC), duo-active-neutral-point-clamped (D-ANPC), and duo-neutral-point-piloted (D-NPP) multilevel voltage-sourced converter topologies. The D-NPC, D-ANPC, and D-NPP converters phase-leg is realized by adding low-frequency semiconductor power switches to their structures. This results in a substantial reduction in the number of the high-frequency pulse-widthmodulation (PWM) insulated-gate bipolar transistors (IGBTs) and clamping passive devices including diodes as well as flying-capacitors (FCs). Moreover, a drastic abatement in the total voltage rating and total stored energy of the FCs within the D-ANPC topology is achieved compared to the classic ANPC configuration. The experimental results are provided for D-NPC, D-ANPC, and D-NPP converters to validate the feasibility of their topology and modulation method for control of the multilevel converters.