With the various applications of the Internet of Things, research into wireless sensor networks (WSNs) has become increasingly important. However, because of their limited energy, the communication abilities of the wireless nodes distributed in the WSN are limited. The main task of WSNs is to collect more data from targets in an energy-efficient way, because the battery replacement of large amounts of nodes is a labor-consuming work. Although the life of WSNs can be prolonged through energy-harvesting (EH) technology, it is necessary to design an energy-efficient routing protocol for the energy harvesting-based wireless sensor networks (EH-WSNs) as the nodes would be unavailable in the energy harvesting phase. A certain number of unavailable nodes would cause a coverage hole, thereby affecting the WSN’s monitoring function of the target environment. In this paper, an adaptive hierarchical-clustering-based routing protocol for EH-WSNs (HCEH-UC) is proposed to achieve uninterrupted coverage of the target region through the distributed adjustment of the data transmission. Firstly, a hierarchical-clustering-based routing protocol is proposed to balance the energy consumption of nodes. Then, a distributed alternation of working modes is proposed to adaptively control the number of nodes in the energy-harvesting mode, which could lead to uninterrupted target coverage. The simulation experimental results verify that the proposed HCEH-UC protocol can prolong the maximal lifetime coverage of WSNs compared with the conventional routing protocol and achieve uninterrupted target coverage using energy-harvesting technology.

The automatic sleep stage classification technique can facilitate the diagnosis of sleep disorders and release the medical expert from labor-consumption work. In this paper, novel improved model based essence features (IMBEFs) were proposed combining locality energy (LE) and dual state space models (DSSMs) for automatic sleep stage detection on single-channel electroencephalograph (EEG) signals. Firstly, each EEG epoch is decomposed into low-level sub-bands (LSBs) and high-level sub-bands (HSBs) by wavelet packet decomposition (WPD), separately. Then, the DSSMs are estimated by the LSBs and the LE calculation is carried out on HSBs. Thirdly, the IMBEFs extracted from the DSSM and LE are fed into the appropriate classifier for sleep stage classification. The performance of the proposed method was evaluated on three public sleep databases. The experimental results show that under the Rechtschaffen’s and Kale’s (R&K) standard, the sleep stage classification accuracies of six classes on the Sleep EDF database and the Dreams Subjects database are 92.04% and 78.92%, respectively. Under the American Academy of Sleep Medicine (AASM) standard, the classification accuracies of five classes in the Dreams Subjects database and the ISRUC database reached 79.90% and 81.65%. The proposed method can be used for reliable sleep stage classification with high accuracy compared with state-of-the-art methods.

The convolutional neural network (CNN) has made great success in many fields, and is gradually being applied in edge-computing systems. Taking the limited budget of the resources in the systems into consideration, the implementation of CNNs on embedded devices is preferred. However, accompanying the increasingly complex CNNs is the huge cost of memory, which constrains its implementation on embedded devices. In this paper, we propose an efficient, pipelined convolution module based on a Brain Floating-Point (BF16) to solve this problem, which is composed of a quantization unit, a serial-to-matrix conversion unit, and a convolution operation unit. The mean error of the convolution module based on BF16 is only 0.1538%, which hardly affects the CNN inference. Additionally, when synthesized at 400 MHz, the area of the BF16 convolution module is 21.23% and 18.54% smaller than that of the INT16 and FP16 convolution modules, respectively. Furthermore, our module using the TSMC 90 nm library can run at 1 GHz by optimizing the critical path. Finally, our module was implemented on the Xilinx PYNQ-Z2 board to evaluate the performance. The experimental results show that at the frequency of 100 MHz, our module is, separately, 783.94 times and 579.35 times faster than the Cortex-M4 with FPU and Hummingbird E203, while maintaining an extremely low error rate.

Pedestrian detection is the key technology in Advanced Driver Assistant System (ADAS).Until recently, pedestrian detection, which is realized as the vehicle equipment, still doesn’t have the mature product. So, this thesis proposes a novel pedestrian detection system on board with the E-HOG (Histogram of Gradient) IP (intellectual property), can be used as the real time vehicle equipment. Three contributions are made in this thesis. Firstly, Sobel operator cascaded Uniform Local Binary Pattern (LBP) and E-HOG is the novel structure of pedestrian detection system. The Sobel operator gives the sliding step of Uniform LBP detection window, without using the results of LBP detection window. Through this operation, the detection speed will be improved. Second, the vehicle equipment of pedestrian detection is self-developed using FPGA as core devices. Third, E-HOG IP, which is promoted based on the HOG, can extract pedestrian or other objects feature. Without sacrifice of accuracy, this pedestrian detection on board deals with 30 fps (640x480 pixels) and can be used as the real-time detection system.