Conventional PI controllers are vulnerable to changes in parameters and are difficult to tune. In this work, an artificial neural network (ANN) based controller is developed for the robust operation of a single-phase modified packed U-cell five-level inverter (MPUC-5) for solar PV application under variable insolation conditions. An MPUC-5 is a converter with a main and an auxiliary dc link of equal magnitude; although five-level operation is also still feasible with different voltages also. The maximum power point (MPP) of a PV array changes with the variation in the solar insolation. This results in a variable voltage at the output of the boost converter while maintaining the load line at the MPP. Consequently, the fundamental value of the output of the MPUC-5 also tends to change. Thus, it is required to produce angles that commit to an ac output voltage with a constant fundamental value and constrained to a minimum total harmonic distortion along with a third-order harmonic mitigation as per the grid codes, irrespective of the change in the dc-link voltages. A genetic algorithm is employed for this purpose. A large dataset is prepared for two-angle and four-angle operation of MPUC-5 under various dc-link voltages and constraints with which an ANN-based controller is trained. A neural network with a hidden layer is trained with the backpropagation technique; and once a correlation is developed, the network can be operated for a wide range of operating conditions. The robustness of the controller is verified through simulation in MATLAB/Simulink environment and validated by experimental emulation in an hardware in loop environment.

This article explores a single-source UXE-type asymmetrical multilevel inverter for its operation on 13-, 11-, and 9-levels with boosted output voltage. The 13- and 11-level operations require a single voltage sensor to maintain the auxiliary dc link at $V_{\text{dc}}/2$ and produce 1.5 and 1.25 boosting using redundant states and exhibit lower capacitor inrush currents. For the 9-level operation, the topology exhibits self-balancing of the dc-link at $V_{\text{dc}}$ and a boosting of 2. With a conventional pulsewidth modulation (PWM) for the 13-level operation, the inverter can drive a predominantly inductive load of 0.35 lagging at unity modulation index. For the 11-level operation, the levels cease to maintain beyond the modulation of 0.95. Thus, a hybrid PWM is proposed to fully utilize the redundant states for the charging of the switched-capacitors and enhance the inverter active load capability in the 13-level mode by 21% at unity modulation index ( $m_a$ ) and address a 0.8 power factor load at the $m_a$ of 0.9. For the 11-level operation, the levels are maintained at any $m_a$ with the hybrid PWM. The operation of the inverter is also verified for nonlinear load. Further, the 9-level operation with twice boosting and self-balancing is presented. The results are verified on MATLAB/Simulink and validated experimentally.

The basic requirement of all the scalar modulation strategies employed for matrix converter, is to define the desired output voltages. The output phase voltages, if not optimized, results in underutilization of semiconductor device ratings. For better utilization, the output reference phase voltages are modified such that the sinusoidal nature of line voltages is not altered. Multiphase drives are in consideration and much work is being done and reported on multiphase matrix converter-based system. New modulation strategies for such systems are being formulated. Most of these new strategies are based on scalar approach; which in contrast to the space vector pulse width modulation, require addition of friendly harmonics in order to achieve optimized output reference phase voltages and maximum utilization of the matrix converter semiconductor switches. On the other hand, in space vector pulse width modulation, the maximum voltages are inherently achieved. This paper presents a generalized theory, explained in mathematical as well as graphical manner, defining the optimized output reference phase voltages for any number of input and output phases, whether odd or even, for m × n matrix converter. Further, this paper also explores the Venturini method for m × n case. It is found that the method is extendable to 3 × n matrix converters only. Finally, a simple and generalized algorithm, applicable to all m × n matrix converter configurations, is discussed. Results for 3 × 5 matrix converter are validated by simulation and experimental results.

Switched-Capacitor multilevel inverters (SCMLI) are being explored for renewable power applications like solar-PV integration because of their benefits of low component count and low-cost factors. This work presents and explores a new multilevel inverter with a hexad voltage-boosting capability. It employs a single source and produces a 13-level waveform by utilizing only fourteen switches, two diodes, and four capacitors. The voltage across the capacitors is maintained at the desired magnitudes during the switching of the inverter by connecting the DC source and capacitors in parallel at several time locations in one operating cycle. The topology proposed in this work is compared with the recent 13-level topologies in terms of switches, diodes, capacitors, and cost factors (CF). A level-shifted PWM-based algorithm generates the circuit switches’ PWM pulses. The CF of the proposed SCMLI is found to be 2.461, which is the lowest among the compared hexad-boosted MLIs. Experimental validation is performed on a hardware prototype to validate various operational conditions of load change, modulation index change, and reference frequency change.

Pulse width modulation (PWM) control for power converters have been vastly investigated and used in many industrial application. For medium voltage and high power applications, low switching frequency PWM techniques are preferred over high switching frequency-based PWM techniques. The preprogrammed low switching frequency-based PWM technique known as selective harmonics elimination (SHE) gives the better quality waveform at a lower switching frequency. The main difficulty in applying SHE PWM is in solving of non-linear transcendental equations for obtaining switching angles. Several methods have been proposed for computation of switching angles that include numerical techniques, optimization techniques, and algebraic techniques. However, the computation of switching angles is still a challenging task in the application of SHE PWM. In this paper, a novel fast convergent homotopy perturbation method (HPM) is proposed to compute switching angles for a multilevel inverter at a faster rate. The solutions obtained by the proposed technique is as accurate as obtained by the algebraic methods with no dependency on the initial guess. The proposed technique can compute the higher number of switching angles with multiple solutions in some modulation index range. A prototype is developed and the computed switching angles have been verified using field-programmable gate arrays (FPGA) controller to validate the results for practical applications.

This article presents an 11-level operation of the WE (Wee)-Type inverter. The topology employs a single DC-source, has a reduced number of components, and exhibits a boosting capability. A voltage balancing algorithm is proposed where the inverter's redundant states are employed to maintain the auxiliary DC-link voltage. It is shown that with the control algorithm, the link voltage is preserved at half the primary DC-link voltage, and the 11-level operation is possible for any load. The presented 11-level WE-type structure is also compared with recent 11-level structures and has a lowest cost factor. Two modulation strategies verify the 11-level operation of the inverter: first, a modified nearest level control (MNLC) with the usage of both zero states is developed; and, second, selective harmonic elimination (SHE) is employed, where the angles are generated using a differential evolution (DE) technique. The maximum efficiency of the inverter is 97.55 %. The performance of the inverter is validated in MATLAB/Simulink and on the hardware-in-the-loop platform.