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Reliability, a crucial requirement in any modern microprocessor, assures correct execution over its lifetime. As mission critical components are becoming common in commodity systems, e.g., control of autonomous cars, the demand for reliable processing continues to grow. The latest process technologies have aggravated the situation by causing microprocessors to be highly vulnerable to reliability concerns. This paper examines the asymmetric aging phenomenon, which is a major reliability worry in advanced process nodes. In this phenomenon, logical elements and memory cells suffer from unequal timing degradation over their lifetimes and, consequently, raise reliability concerns. Thus far, most studies approached asymmetric aging from a circuit or physical design viewpoint, but these solutions were quite limited and suboptimal. In this paper, we introduce an asymmetric aging-aware microarchitecture that aims to reduce the phenomenon's impact. The study is mainly focused on the following subsystems: execution units, register files and memory hierarchy. Our experiments indicate that the proposed solutions incur minimal overhead while significantly mitigating asymmetric aging stress.
Freddy Gabbay; Avi Mendelson. Asymmetric aging effect on modern microprocessors. Microelectronics Reliability 2021, 119, 114090 .
AMA StyleFreddy Gabbay, Avi Mendelson. Asymmetric aging effect on modern microprocessors. Microelectronics Reliability. 2021; 119 ():114090.
Chicago/Turabian StyleFreddy Gabbay; Avi Mendelson. 2021. "Asymmetric aging effect on modern microprocessors." Microelectronics Reliability 119, no. : 114090.
The demand for running NNs in embedded environments has increased significantly in recent years due to the significant success of convolutional neural network (CNN) approaches in various tasks, including image recognition and generation. The task of achieving high accuracy on resource-restricted devices, however, is still considered to be challenging, which is mainly due to the vast number of design parameters that need to be balanced. While the quantization of CNN parameters leads to a reduction of power and area, it can also generate unexpected changes in the balance between communication and computation. This change is hard to evaluate, and the lack of balance may lead to lower utilization of either memory bandwidth or computational resources, thereby reducing performance. This paper introduces a hardware performance analysis framework for identifying bottlenecks in the early stages of CNN hardware design. We demonstrate how the proposed method can help in evaluating different architecture alternatives of resource-restricted CNN accelerators (e.g., part of real-time embedded systems) early in design stages and, thus, prevent making design mistakes.
Alex Karbachevsky; Chaim Baskin; Evgenii Zheltonozhskii; Yevgeny Yermolin; Freddy Gabbay; Alex Bronstein; Avi Mendelson. Early-Stage Neural Network Hardware Performance Analysis. Sustainability 2021, 13, 717 .
AMA StyleAlex Karbachevsky, Chaim Baskin, Evgenii Zheltonozhskii, Yevgeny Yermolin, Freddy Gabbay, Alex Bronstein, Avi Mendelson. Early-Stage Neural Network Hardware Performance Analysis. Sustainability. 2021; 13 (2):717.
Chicago/Turabian StyleAlex Karbachevsky; Chaim Baskin; Evgenii Zheltonozhskii; Yevgeny Yermolin; Freddy Gabbay; Alex Bronstein; Avi Mendelson. 2021. "Early-Stage Neural Network Hardware Performance Analysis." Sustainability 13, no. 2: 717.