The EARtH algorithm finds the optimal voltage and frequency operational point of the processor in order to achieve minimum energy of the computing platform. The algorithm is based on a theoretical model employing a small number of parameters, which are extracted from real systems using off-line and run-time methods. The model and algorithm have been validated on real systems using 45nm, 32nm and 22nm Intel® Core processors. The algorithm can save up to 44% energy compared with the commonly used fixed frequency policies.

The rising tide of attacks, in the recent years, against microprocessors and the system-on-chip (SoC) space as a whole, has led to a growing number of studies into security of SoCs. Security fortification is often incorporated as a follow-up feature to existing systems and many vulnerabilities cannot be patched without significantly degrading performance. A holistic approach to address the security challenge needs to include security-first design principles, security-aware test and verification methodologies, and well-quantified performance trade-off analysis. In this paper, we report the design principles of ITUS ¹ , a secure SoC based on RISC-V architecture. In parallel, a systematic overview of various design and automation efforts towards achieving SoC security is presented. ¹ after Itus, a relevant name from Greek mythology