George Charitopoulos

Dr. George Charitopoulos


Research Focus & Metrics

Academic Career Length

12Years (2015-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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11 February 2021 in Electronics
Verified
Journal Article
Open access
PDF file
GCGeorge Charitopoulos
George Charitopoulos
Ioannis PapaefstathiouIoannis Papaefstathiou
Ioannis Papaefstathiou
DPDionisios Pnevmatikatos
Dionisios Pnevmatikatos
Executing complex scientific applications on Coarse Grain Reconfigurable Arrays (CGRAs) offers improvements in the execution time and/or energy consumption when compared to optimized software implementations or even fully customized hardware solutions. In this work, we explore the potential of application analysis methods in such customized hardware solutions. We offer analysis metrics from various scientific applications and tailor the results that are to be used by MC-Def, a novel Mixed-CGRA Definition Framework targeting a Mixed-CGRA architecture that leverages the advantages of CGRAs and those of FPGAs by utilizing a customized cell-array along, with a separate LUT array being used for adaptability. Additionally, we present the implementation results regarding the VHDL-created hardware implementations of our CGRA cell concerning various scientific applications.

1 October 2015
Verified
Conference Paper
Open access
CCCatalin Bogdan Ciobanu
Catalin Bogdan Ciobanu
AVAna Lucia Varbanescu
Ana Lucia Varbanescu
DPDionisios Pnevmatikatos
Dionisios Pnevmatikatos
GCGeorge Charitopoulos
George Charitopoulos
XNXinyu Niu
Xinyu Niu
DSDirk Stroobandt
Dirk Stroobandt
To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application features can be optimally accelerated, even if they regularly change over time. In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental feature instead of an add-on. EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a central design concept, and applications that are tuned to maximally benefit from the proposed run-time reconfiguration techniques. Ultimately, this open platform will improve Europe's competitive advantage and leadership in the field.

25 March 2020
Verified
Book Chapter
Closed access
PDF file
GCGeorge Charitopoulos
George Charitopoulos
DPDionisios Pnevmatikatos
Dionisios Pnevmatikatos