The growing use of Cyber-Physical Systems (CPS) in a plethora of domains (e.g. healthcare, industry, smart homes, transportation, etc.) triggers an urgent demand for simulation frameworks that can simulate in an integrated manner all the components (i.e. CPUs, Memories, Networks, Physical Environment) of a system-under-design(SuD). By utilizing such a simulator, software design can proceed in parallel with physical development which results in the reduction of the so important time-to-market. The main problem, however, is that currently there is a shortage of such simulation frameworks; most simulators used for modelling the digital aspects of CPS applications (i.e. full-system CPU/Mem/Peripheral simulators) lack any support of the CPS physical aspects and vice versa. The presented fully-distributed simulation framework (APOLLON) is the first known open-source, high-performance simulator that can handle holistically complex CPSs including processors, peripherals, networks and physical aspects of them. APOLLON is an extension of the COSSIM simulation framework and it integrates, in a novel and efficient way, a combined processing and network simulator with the widely-used Ptolemy physical simulator, in a transparent way. Our highly integrated approach is further augmented with Machine Learning capabilities by implementing Long Short-Term Memory (LSTM) and Gated Recurrent Unit (GRU) recurrent neural networks in both the Cyber and Physical domains, enabling users to develop their complex recurrent neural networks significantly fast and accurately. APOLLON has been evaluated when executing a number of benchmarks and real-world use cases; the end results demonstrate that the presented approach has up to 99% accuracy in the reported SuD aspects.

This paper introduces a novel electroencephalogram (EEG) data classification scheme together with its implementation in hardware using an innovative approach. The proposed scheme integrates into a single, end-to-end trainable model a spatial filtering technique and a neural network based classifier. The spatial filters, as well as, the coefficients of the neural network classifier are simultaneously estimated during training. By using different time-locked spatial filters, we introduce for the first time the notion of "attention" in EEG processing, which allows for the efficient capturing of the temporal dependencies and/ or variability of the EEG sequential data. One of the most important benefits of our approach is that the proposed classifier is able to construct highly discriminative features directly from raw EEG data and, at the same time, to exploit the function approximation properties of neural networks, in order to produce highly accurate classification results. The evaluation of the proposed methodology, using public available EEG datasets, indicates that it outperforms the standard EEG classification approach based on filtering and classification as two separated steps. Moreover, we present a prototype implementation of the proposed scheme in state-of-the-art reconfigurable hardware; our novel implementation outperforms by more than an order of magnitude, in terms of power efficiency, the conventional CPU-based approaches.

As computing becomes ubiquitous, researchers and engineers aim to exploit the potential of the pervasive systems in order to introduce new types of services and address inveterate and emerging problems. This process will, eventually, lead us to the era of urban computing and the Internet of Things; the ultimate goal being to improve our quality of life. But these concepts typically require direct and constant interaction of computing systems with the physical world in order to be realized, which inevitably leads to the introduction of a range of safety and privacy issues that must be addressed. One such important aspect is the fine-grained control of access to the resources of these pervasive embedded systems, in a secure and scalable manner. This paper presents an implementation of such a secure policy-based access control scheme, focusing on the use of well-established, standardized technologies and considering the potential resource-constraints of the target heterogeneous embedded devices. The proposed framework adopts a DPWS-compliant approach for smart devices and introduces XACML-based access control mechanisms. The proof-of-concept implementation is presented in detail, along with a performance evaluation on typical embedded platforms.

As the telecommunications industry recovers from the severe downturn of recent years, data traffic continues to exhibit a rate of increase that outpaces advances in VLSI technology. Therefore, lowering overall system cost at network processing nodes and maximizing network utilization - hence revenues - remain extremely important objectives. To address these issues, new semiconductor devices called network processing units (NPUs) have emerged. They are optimized to provide programmable processing of protocol data units (PDUs) in networks with diverse requirements while efficiently supporting current and emerging protocols and services. NPUs promise to deliver an ASICs speed with a CPU's programmability, thus augmenting the capacity and features of network nodes that forward and manipulate data traffic. The Programmable Protocol Processor (PRO3) system reduces the overhead incurred by common "BRUTE-FORCE" architectures by using the least-required hardware resources for certain common well-defined tasks.

Executing complex scientific applications on Coarse Grain Reconfigurable Arrays (CGRAs) offers improvements in the execution time and/or energy consumption when compared to optimized software implementations or even fully customized hardware solutions. In this work, we explore the potential of application analysis methods in such customized hardware solutions. We offer analysis metrics from various scientific applications and tailor the results that are to be used by MC-Def, a novel Mixed-CGRA Definition Framework targeting a Mixed-CGRA architecture that leverages the advantages of CGRAs and those of FPGAs by utilizing a customized cell-array along, with a separate LUT array being used for adaptability. Additionally, we present the implementation results regarding the VHDL-created hardware implementations of our CGRA cell concerning various scientific applications.