This paper presents a charge-domain in-memory computing (IMC) macro for precision-scalable deep neural network accelerators. The proposed Dual-SRAM cell structure with coupling capacitors enables charge-domain multiply and accumulate (MAC) operation with variable-precision signed weights. Unlike prior charge-domain IMC macros that only support binary neural networks or digitally compute weighted sums for MAC operation with multi-bit weights, the proposed macro implements analog weighted sums for energy-efficient bit-scalable MAC operations with a novel series-coupled merging scheme. A test chip with a 16-kb SRAM macro is fabricated in 28-nm FDSOI process, and the measured macro throughput is 125.2-876.5 GOPS for weight bit-precision varying from 2 to 8. The macro also achieves energy efficiency ranging from 18.4 TOPS/W for 8-b weight to 119.2 TOPS/W for 2-b weight.

This paper investigates the power and performance trade-offs associated with integrating deep neural network (DNN) computation in an image sensor. The paper presents the design of Neurosensor-a CMOS image sensor with 3-D stacking of pixel array, read-out circuits, memory, and computing logic for DNN. The analysis shows integrating DNN reduces transmit latency (and energy), but at the expense of processing and memory access latency (and energy). Hence, given a specific DNN and transmission bandwidth, there exist an optimal number of layers that should be computed in the sensor to maximize energy-efficiency. In general, it is often more efficient to integrate memory within the sensor stack and/or implement only the feature extraction layers on the sensor, and optimized configurations can achieve up to 90× improvement in energy efficiency compared to the baseline. Further, coupled power, thermal, and noise simulation demonstrates that integrating DNN computation can increase pixel-array temperature resulting in higher noise, and hence, lower classification accuracy.

Design of ultralightweight but secure encryption engine is a key challenge for Internet-of-Things edge devices. This paper explores the system level design space for an ultralow power image sensor node for secure communication and proposes an optimized datapath architecture for 128-bit SIMON (SIMON128), a lightweight block cipher, for minimal performance, power, and area overheads with increased level of side-channel security. Various datapath architectures for SIMON are explored for simultaneously increasing energy-efficiency and resistance to power-based side-channel analysis (PSCA) attacks. Alternative datapath architectures are implemented on ASIC (15 nm CMOS) and field programmable gate array (FPGA) (Spartan-6, 45 nm) to perform power, performance, and area analysis. We show that, although a bitserial datapath minimizes area and power, a round unrolled datapath provides 80× higher energy-efficiency and 143× higher performance, compared to the baseline bitserial design. Moreover, the PSCA measurements performed using Sakura-G board with Spartan-6 FPGA, demonstrate that a 6-round unrolled datapath improves minimum-traces-to-disclosure for correlation power analysis (CPA) by at least 384× over baseline bitserial design with no successful CPA even with 500000 measurements. Finally, application to the image-sensor node demonstrates that optimized unrolled SIMON128 can provide equivalent performance to AES128 at lower area, higher energy efficiency, and improved side channel security.

A typical semi-supervised learning-based scheme is based on training a single model for labeled data. For unlabeled data, it uses the pseudo-labeling method to obtain labels. However, the samples during pseudo-labeling are often filtered using a probability threshold, which suffers from the challenge of effective threshold selection. In the case of a high probability threshold, correct samples may not be labeled, and in the case of a low threshold, samples can be wrongly labeled. This threshold issue degrades the overall performance of the model. This paper addresses this vital issue by proposing a novel approach of SSL named Binary-Classifiers-Enabled Filters for Semi-Supervised Learning (BSSL) for labeling the unlabeled data by using binary classifiers as data filters. That is, we train binary classifiers dedicated to each class. After training, we propose three methods for labeling the unlabeled data; cascading, non-cascading, and rank-based binary classifiers. Our extensive experiment shows rank-based binary classifiers are the best choice for labeling the data. Our approach eliminates threshold selection to improve the performance of the model. Comprehensive experiments are performed to demonstrate the effectiveness of our approach on a variety of domains, including image classification, text classification and audio classification, datasets including MNIST, fashion-MNIST, EuroSat, ESC10, Free Spoken Digit dataset, Audio Emotion recognition, reuter and mice protein dataset. Rank based binary classifiers (BSSL) approach achieves absolute performance of atleast 10% and 5% over supervised learning(SL) and SSL, respectively on audio datasets in different number of sample cases except RAVDESS dataset. Moreover, BSSL shows tremendous performance on image datasets specifically when number of samples is very small. Overall, BSSL outperformed the purely supervised learning approach and SSL pseudo-labeling approaches in different number of samples cases.