We propose a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. A conventional approach to generate these currents is to drop a temperature sensitive voltage across a resistor. Since a large resistance is required to achieve nWs of power consumption with typical voltage levels (100 s of mV to 1 V), we introduce a new sensing element that outputs only 75 mV to save both power and area. The sensor is implemented in 0.18 μm CMOS and occupies 0.09 mm ² while consuming 71 nW. After 2-point calibration, an inaccuracy of + 1.5°C/-1.4°C is achieved across 0 °C to 100 °C. With a conversion time of 30 ms, 0.3 °C (rms) resolution is achieved. The sensor does not require any external references and consumes 2.2 nJ per conversion. The sensor is integrated into a wireless sensor node to demonstrate its operation at a system level.

A 1.0 mm³ general-purpose sensor node platform with heterogeneous multi-layer structure is proposed. The sensor platform benefits from modularity by allowing the addition/removal of IC layers. A new low power I²C interface is introduced for energy efficient inter-layer communication with compatibility to commercial I²C protocols. A self-adapting power management unit is proposed for efficient battery voltage down conversion for wide range of battery voltages and load current. The power management unit also adapts itself by monitoring energy harvesting conditions and harvesting sources and is capable of harvesting from solar, thermal and microbial fuel cells. An optical wakeup receiver is proposed for sensor node programming and synchronization with 228 pW standby power. The system also includes two processors, timer, temperature sensor, and low-power imager. Standby power of the system is 11 nW.

A syringe-implantable electrocardiography (ECG) monitoring system is proposed. The noise optimization and circuit techniques in the analog front-end (AFE) enable 31 nA current consumption while a minimum energy computation approach in the digital back-end reduces digital energy consumption by 40%. The proposed SoC is fabricated in 65 nm CMOS and consumes 64 nW while successfully detecting atrial fibrillation arrhythmia and storing the irregular waveform in memory in experiments using an ECG simulator, a live sheep, and an isolated sheep heart.

Recent progress in ultra-low-power circuit design is creating new opportunities for cubic millimeter computing. Robust low-voltage operation has reduced active mode power consumption considerably, but standby mode power consumption has received relatively little attention from low-voltage designers. In this work, we describe a low-voltage processor called the Phoenix Processor that has been designed at the device, circuit, and architecture levels to minimize standby power. A test chip has been implemented in a carefully selected 0.18 mum process in an area of only 915 times 915 mum². Measurements show that Phoenix consumes 35.4 pW in standby mode and 226 nW in active mode.

This paper presents a fully integrated energy harvester that maintains >35% end-to-end efficiency when harvesting from a 0.84 mm ² solar cell in low light condition of 260 lux, converting 7 nW input power from 250 mV to 4 V. Newly proposed self-oscillating switched-capacitor (SC) DC-DC voltage doublers are cascaded to form a complete harvester, with configurable overall conversion ratio from 9× to 23×. In each voltage doubler, the oscillator is completely internalized within the SC network, eliminating clock generation and level shifting power overheads. A single doubler has >70% measured efficiency across 1 nA to 0.35 mA output current ( >10 ⁵ range) with low idle power consumption of 170 pW. In the harvester, each doubler has independent frequency modulation to maintain its optimum conversion efficiency, enabling optimization of harvester overall conversion efficiency. A leakage-based delay element provides energy-efficient frequency control over a wide range, enabling low idle power consumption and a wide load range with optimum conversion efficiency. The harvester delivers 5 nW-5 μW output power with >40% efficiency and has an idle power consumption 3 nW, in test chip fabricated in 0.18 μm CMOS technology.