The superior electro-thermal properties of silicon carbide (SiC) power devices permit higher temperature of operation and enable higher power density compared with silicon devices. Nevertheless, the reliability of SiC power modules has been identified as a major area of uncertainty in applications which require high reliability. Traditional power module packaging methods developed for silicon chips have been adopted for SiC and the different thermomechanical properties cause different fatigue stresses on the solder layer of the chip. In this paper, a 2-D finite element model has been developed to evaluate the stress performance and lifetime of the solder layer for Si devices, which has been validated using accelerated power cycling tests on Si IGBTs. The proposed model was extrapolated for SiC devices of the same voltage and current rating using the same solder material and the results show that under the same cyclic power loss profile the induced stress and strain energy in the die attach layer is much higher and concentrates on the die/solder interfacial area for SiC chips. Using the validated stress-based model, the lifetime can be quantified when SiC chips are used. This ability to extrapolate the available power cycling and lifetime data of silicon chips to SiC chips would be a key element for developing reliable packaging methods for SiC devices.

The future of power conversion at low-to-medium voltages (around 650V) poses a very interesting debate. At low voltages (below 100V), the silicon MOSFET reigns supreme and at the higher end of the automotive medium voltage application spectrum (approximately 1 kV and above) the SiC power MOSFET looks set to topple the dominance of the silicon IGBT. At very high voltages (4.5 kV, 6.5 kV and above) used for grid applications, the press-pack thyristor remains undisputed for current source converters and the press-pack IGBTs for voltage source converters. However, around 650 V, there does not seem to be a clear choice with all the major device manufacturers releasing different technology variants ranging from SiC Trench MOSFETs, SiC Planar MOSFETs, cascode-driven WBG FETs, silicon NPT and Field-stop IGBTs, silicon super-junction MOSFETs, standard silicon MOSFETs and enhancement mode GaN HEMTs. Each technology comes with its unique selling point with GaN being well known for ultra-high speed and compact integration, SiC is well known for high temperature, electro-thermal ruggedness and fast switching while silicon remains clearly dominant in cost and proven reliability. This review comparatively assesses the performance of some of these technologies, investigates their body diodes, discusses device reliability and avalanche ruggedness.

The temperature and dV/dt dependence of crosstalk has been analyzed for Si-IGBT and SiC-MOSFET power modules. Due to a smaller Miller capacitance resulting from a smaller die area, the SiC module exhibits smaller shoot-through currents compared with similarly rated Si-IGBT modules in spite of switching with a higher dV/dt and with a lower threshold voltage. However, due to high voltage overshoots and ringing from the SiC Schottky diode, SiC modules exhibit higher shoot-through energy density and induce voltage oscillations in the dc link. Measurements show that the shoot-through current exhibits a positive temperature coefficient for both technologies, the magnitude of which is higher for the Si-IGBT, i.e., the shoot-through current and energy show better temperature stability in the SiC power module. The effectiveness of common techniques of mitigating shoot-through, including bipolar gate drives, multiple gate resistance switching paths, and external gate-source and snubber capacitors, has been evaluated for both technologies at different temperatures and switching rates. The results show that solutions are less effective for SiC-MOSFETs because of lower threshold voltages and smaller margins for negative gate bias on the SiC-MOSFET gate. Models for evaluating the parasitic voltage have also been developed for diagnostic and predictive purposes. These results are important for converter designers seeking to use SiC technology.

This paper examines dynamic temperature-sensitive electrical parameters (TSEPs) for SiC MOSFETs. It is shown that the switching rate of the output current (dI _{D S} /dt) coupled with the gate current plateau (I _{G P} ) during turn-ON could be an effective TSEP under specific operating conditions. Both parameters increase with the junction temperature of the device as a result of the negative temperature coefficient of the threshold voltage. The temperature dependency of dI _DS /dt has been shown to increase with the device current rating (due to larger input capacitance) and external gate resistance (R _G ^EXT ). However, as dI _{D S} /dt is increased by using a small R _G ^EXT , parasitic inductance suppresses the temperature sensitivity of the drain and gate current transients by reducing the “effective gate voltage” on the device. Since the temperature sensitivity of dI _{D S} /dt is at the highest with maximum R _G ^EXT , there is a penalty from higher switching losses when this method is used in real time for junction temperature sensing. This paper investigates and models the temperature dependency of the gate and drain current transients as potential TSEPs for SiC power MOSFETs.

Operational management for reliability of power electronic converters requires sensitive condition monitoring and accurate lifetime modeling. This study adds to the second aspect by examining the effect of cyclic junction temperature variations ΔT _j of low amplitude in different stages of the power module ageing process. It is found that such relatively minor stress cycles, which happen frequently during normal operation, may not be able to directly initiate a crack but can contribute to the development of damage due to stress concentration. This agrees with the observation that the ageing process tends to accelerate toward the end of life. This study investigates the dependence of the ageing effect on the amplitude of ΔT _j , the mean junction temperature T,,,, and the present health condition of the module, and proposes a lifetime model focusing on die-attach solder fatigue. It is assumed that the future-ageing process is independent of the operational history that has led to the current state of health. The model is intended for operational management of converter systems that are subjected to frequent low ΔT _j stress cycles and are supposed to be in service reliably for a long time with a slow ageing process. Experimental results validate the model.

This paper presents a series of experiment results on the ageing effects of cyclic junction temperature variations (ΔT _j ) of low amplitudes in power modules, to help the capturing of module reliability characteristics and the derivation of lifetime models in the future. Power cycling tests, for nonaged and aged modules, are designed to illustrate the failure mechanisms. Insulated gate bipolar transistor (IGBT) modules in actual converters are usually operated in a ΔT _j range up to 40 °C; therefore, tests are carried out to observe the effects of such narrow ΔT _j stress cycles on the module lifetime. It is found that the relatively minor stress cycles may not be able to directly initiate a crack but can contribute to the development of damage in the die attach solder layer due to stress concentration. Finite element analysis modeling is utilized to verify the stress concentration effect. The experiment results show that the effects of the narrow ΔT _j stress cycles are affected by the ageing status of the module and the stress level itself.