Matrix-Vector Multiplications (MVMs) represent a heavy workload for both training and inference in Deep Neural Networks (DNNs) applications. Analog In-memory Computing (AIMC) systems based on Phase Change Memory (PCM) has been shown to be a valid competitor to enhance the energy efficiency of DNN accelerators. Although DNNs are quite resilient to computation inaccuracies, PCM non-idealities could strongly affect MVM operations precision, and thus the accuracy of DNNs. In this paper, a combined hardware and software solution to mitigate the impact of PCM non-idealities is presented. The drift of PCM cells conductance is compensated at the circuit level through the introduction of a conductance ratio at the core of the MVM computation. A model of the behaviour of PCM cells is employed to develop a device-aware training for DNNs and the accuracy is estimated in a CIFAR-10 classification task. This work is supported by a PCM-based AIMC prototype, designed in a 90-nm STMicroelectronics technology, and conceived to perform Multiply-and-Accumulate (MAC) computations, which are the kernel of MVMs. Results show that the MAC computation accuracy is around 95% even under the effect of cells drift. The use of a device-aware DNN training makes the networks less sensitive to weight variability, with a 15% increase in classification accuracy over a conventionally-trained Lenet-5 DNN, and a 36% gain when drift compensation is applied.

This paper presents a readout scheme for Analog In-memory Computing (AIMC) based on an embedded Phase-change Memory (ePCM). Conductance time drift is overcome with a hardware compensation technique based on a reference cell conductance tracking (RCCT). Accuracy drop due to circuits mismatch and variability involved in the computational chain are minimized with an optimized iterative program-and-verify algorithm applied to the PCM devices. The proposed AIMC scheme is designed and manufactured in a 90-nm STMicroelectronics CMOS technology, with the aim of adding a signed Multiply-and-Accumulate (MAC) computation feature to a Ge-rich GeSbTe (GST) embedded PCM array. Experimental characterizations are performed under different operating conditions, and show that mean MAC decrease in time is approximately null at room temperature and reduced by a factor of 3 after 64-hours bake at 85∘C. Based on several MAC operations, the estimated 512×512 Matrix-Vector-Multiplication (MVM) accuracy is 97.4%, whose decrease in time is less than 3% in the worst case.

Phase Change Memory (PCM) has emerged as a promising non-volatile memory technology with significant applications in both edge computing and analog in-memory computing. This paper synthesizes recent research contributions on the use of PCM for smart sensing, structural health monitoring, neural network acceleration, and binary pattern matching. By examining key advancements, challenges, and potential future developments, this work provides a comprehensive state-of-the-art overview of PCM in these domains, highlighting the possible employments of PCM technology in further edge computing scenarios including medical and human body monitoring.

In this paper, a thorough characterization of phase-change memory (PCM) cells was carried out, aimed at evaluating and optimizing their performance as enabling devices for analog in-memory computing (AIMC) applications. Exploiting the features of programming pulses, we discuss strategies to reduce undesired phenomena that afflict PCM cells and are particularly harmful in analog computations, such as low-frequency noise, time drift, and cell-to-cell variability of the conductance. The test vehicle is an embedded PCM (ePCM) provided by STMicroelectronics and designed in 90-nm smart power BCD technology with a Ge-rich Ge-Sb-Te (GST) alloy for automotive applications. On the basis of the results of the characterization of a large number of cells, we propose an iterative algorithm to allow multi-level cell conductance programming, and its performances for AIMC applications are discussed. Results for a group of 512 cells programmed with four different conductance levels are presented, showing an initial conductance spread under 6%, relative current noise less than 9% in most cases, and a relative conductance drift of 15% in the worst case after 14 h from the application of the programming sequence.

Smart devices for structural health monitoring provide edge computing capabilities to reduce wireless transmission and, thus, power consumption. Although effective algorithms have been proposed in the last few decades, traditional microcontrollers require heavy data flow between the memory and the central processing unit that involves a considerable fraction of the total energy consumption. Phase change memory has recently emerged as an attractive solution in the field of resistive nonvolatile memory for analog in-memory computing, which is a valid approach to avoid data being conveyed among distinct elaboration units. However, it has never been envisaged in structural health monitoring applications. As this technology is still in an embryonic state, several challenges related to nonlinearities and nonidealities of the memory elements and the energy expenditure related to the memory reprogramming process may undermine its usage. In this paper, the application of a novel identification approach for civil infrastructures is investigated using phase change memories. The main computational core of the presented algorithm, consisting of one-dimensional convolutions, is particularly suitable for implementations involving analog in-memory computing, thus showing the great potential of this technology for structural health monitoring applications. The test unit is an embedded phase change memory provided by STMicroelectronics and designed in 90-nm smart power bipolar complementary metal-oxide-semiconductor (CMOS)-double-diffused metal-oxide-semiconductor (DMOS) technology with a Ge-rich Ge-Sb-Te alloy for automotive applications. Experimental results obtained for a viaduct of an Italian motorway support the efficacy of the method. Moreover, the influence of nonidealities on the outcomes of damage identification based on both dynamic and quasi-static structural parameters is examined.

This article introduces a method to mitigate conductance time drift of phase-change memory (PCM) cells for improved resilience of matrix-vector multiplication (MVM) in analog in-memory computing (AIMC) systems. The proposed approach consists of on-chip current-induced annealing of each PCM device to stabilize its conductance at a target level, avoiding any rearrangement of the cell lattice. The procedure is performed within the programming phase of PCM devices with no severe constraints on execution time because of the infrequent update of MVM weights in deep neural networks (DNNs). Experimental validations were conducted on a 90-nm STMicroelectronics CMOS Ge-rich GeSbTe (GST)-embedded PCM targeting 16 conductance levels, and results indicate that the average time drift and variability of cells conductance are reduced by at least a factor of 2.3 and 3.5, respectively, compared with standard programming. Simulations based on empirical results reveal a 0.8% MVM accuracy loss after 12 h at room temperature and 4.8% after an additional 64-h bake at 85 $^{\circ}$ C, with a considerable increase in MVM computing retention compared with those granted with standard programming. Accuracy loss is minimized to around 1% even at high temperatures when the proposed method is combined with hardware drift compensation.