Phase Change Memory (PCM) has emerged as a promising non-volatile memory technology with significant applications in both edge computing and analog in-memory computing. This paper synthesizes recent research contributions on the use of PCM for smart sensing, structural health monitoring, neural network acceleration, and binary pattern matching. By examining key advancements, challenges, and potential future developments, this work provides a comprehensive state-of-the-art overview of PCM in these domains, highlighting the possible employments of PCM technology in further edge computing scenarios including medical and human body monitoring.

This article presents a high-precision close-to-analog programming methodology for phase-change memory (PCM) cells, targeting analog in-memory computing (AiMC) architectures for edge-artificial intelligence (AI) applications. By leveraging an iterative accumulation approach during the verify phase, the proposed technique enhances the effective number of bits (ENOBs) achievable in PCM cells. Experimental validation on a 28-nm STMicroelectronics FD-SOI PCM-based AiMC macro demonstrates the capability to accurately program large-scale matrix-vector multiplication (MVM) weights. The results highlight the potential of the proposed programming scheme to overcome intrinsic device variability, resulting in high accuracy in MVM computation. The methodology also shows promising applicability for mapping deep neural network (DNN) and large language model (LLM) weights with high precision, reaching an ENOB of 10.5.

This brief presents a design technique to linearize the frequency-to-conductance characteristic of a Current-Controlled Oscillator (CCO) within a CCO-based ADC used for Matrix-Vector Multiplication (MVM) in Analog in-Memory Computing (AiMC) accelerators. The proposed linearization is achieved by leveraging a bitline voltage regulator (BLVR), a circuit commonly employed to bias the bitlines (BLs) of computational resistive memory arrays. The BLVR utilizes a resistor and a copy of the bitline current to create a feedback mechanism that dynamically adjusts the bitline voltage in response to changes in the total bitline conductance ( $\boldsymbol {g_{BL}}$ ). This feedback reduces the oscillation period by an amount that linearizes the relationship between the CCO output frequency ( $\boldsymbol {f_{CCO}}$ ) and $\boldsymbol {g_{BL}}$ . Simulations in 28 nm FD-SOI technology demonstrate that the proposed BLVR reduces the quadratic coefficient $\boldsymbol {k_{2}}$ of a polynomial approximation of the $\boldsymbol {f_{CCO}}$ – $\boldsymbol {g_{BL}}$ characteristic from $\boldsymbol {5.88\times 10^{-2}}$ to $\boldsymbol {2.31\times 10^{-2}}$ , corresponding to a $\boldsymbol {2.5\times }$ improvement in linearity in the full conductance range.