A vehicular ad hoc network (VANET) has significantly improved transportation efficiency with efficient traffic management, driving safety, and delivering emergency messages. However, existing IP-based VANETs encounter numerous challenges, like security, mobility, caching, and routing. To cope with these limitations, named data networking (NDN) has gained significant attention as an alternative solution to TCP/IP in VANET. NDN offers promising features, like intermittent connectivity support, named-based routing, and in-network content caching. Nevertheless, NDN in VANET is vulnerable to a variety of attacks. On top of attacks, an interest flooding attack (IFA) is one of the most critical attacks. The IFA targets intermediate nodes with a storm of unsatisfying interest requests and saturates network resources such as the Pending Interest Table (PIT). Unlike traditional rule-based statistical approaches, this study detects and prevents attacker vehicles by exploiting a machine learning (ML) binary classification system at roadside units (RSUs). In this connection, we employed and compared the accuracy of five (5) ML classifiers: logistic regression (LR), decision tree (DT), K-nearest neighbor (KNN), random forest (RF), and Gaussian naïve Bayes (GNB) on a publicly available dataset implemented on the ndnSIM simulator. The experimental results demonstrate that the RF classifier achieved the highest accuracy (94%) in detecting IFA vehicles. On the other hand, we evaluated an attack prevention system on Python that enables intermediate vehicles to accept or reject interest requests based on the legitimacy of vehicles. Thus, our proposed IFA detection technique contributes to detecting and preventing attacker vehicles from compromising the network resources.

This paper proposes a novel architecture for multi-core processors, tailored for high-performance parallel computing. The architecture is founded on the innovative notion that complex problems can be decomposed into three relatively independent sub-problems: data processing, data management, and data communication. It features a grid of small, programmable processing units intricately connected to their three neighbouring units, forming a physically scalable and fractal environment. With flexibility, modularity, and scalability as focal points, this architecture aims to address the anticipated real-time signal processing demands in future telecommunication and multimedia systems. One notable aspect of the proposed architecture is its direct support for object-oriented features at the hardware level. Adopting a hybrid approach with Scratchpad Memory (SPM) combined with Cache in the on-chip memory hierarchy enhances performance and adaptability for sophisticated multi-core applications. The study highlights SPM management and introduces a dynamic data management framework. Unlike traditional SPM allocation methods relying on compiler or profiling knowledge, the proposed approach leverages random sampling and probability theory to predict hot-access data during runtime. This dynamic memory access pattern guides SPM allocation, ensuring optimal utilization of SPM's advantages in access speed and energy consumption, complemented by hardware support from DataUnit. This paper presents a paradigm shift in multi-core processor architecture, offering advanced features to meet the evolving requirements of parallel computing, making it well-suited for future telecommunication and multimedia systems. This paper introduces a revolutionary multicore processor architecture designed for high-performance parallel computing. The foundation of the proposed architecture lies in the innovative concept that complex problems can be decomposed into three relatively independent sub-problems: data processing, data management, and data communication. The architecture features a grid of small, programmable processing units, each intricately connected to its three neighboring units, forming a physically scalable and fractal environment. With a focus on flexibility, modularity, and scalability, this architecture addresses the real-time signal processing demands anticipated in future telecommunication and multimedia systems. One distinctive aspect of the proposed architecture is its direct support for object-oriented features at the hardware level. The on-chip memory hierarchy adopts a hybrid approach with Scratchpad Memory (SPM) combined with Cache, enhancing performance and adaptability for sophisticated multi-core applications. The study emphasizes SPM management and introduces a dynamic data management framework. In contrast to traditional SPM allocation methods relying on compiler or profiling knowledge, the proposed approach leverages random sampling and probability theory to predict hot-access data during runtime. This dynamic memory access pattern guides SPM allocation, ensuring optimal utilization of SPM's advantages in access speed and energy consumption, complemented by hardware support from DataUnit. This paper presents a paradigm shift in multicore processor architecture, offering advanced features to meet the evolving requirements of parallel computing, making it well-suited for future telecommunication and multimedia systems

Traditional compiler-based SPM management often fails to accurately predict the memory access characteristics of system scheduling and task switching in a Multi-core Processor environment, thus affecting the effect of SPM management. The use of runtime dynamic detection can make up for this flaw and provide an accurate and efficient dynamic management method. This research focuses on the analysis of the similarities and differences between SPM management in Multi-core Processor environment and single-task environment, and builds a real-time operating system (RTOS) supporting multi-task scheduling according to experimental requirements, which is necessary for the random sampling of SPM allocation algorithm and improvements to meet the needs of adaptive SPM allocation for program runtime in a Multi-core Processor environment. The performance of the random sampling algorithm in Multi-core Processor environment is analyzed which proves the effectiveness of the allocation algorithm for Multi-core Processor environment.

Agricultural logistics is critical for ensuring the timely delivery of fresh produce from farms to markets. However, traditional systems in developing regions often suffer from delays, communication barriers, and limited information access. These inefficiencies lead to post-harvest losses, higher costs, and reduced farmer profitability. With the advent of Industry 4.0, smart logistics services powered by Information and Communication Technologies (ICT), the Internet of Things, cloud computing, and mobile applications offer sustainable solutions. This review examines the role of web- and smartphone-based platforms in the transformation of Pakistan’s agricultural logistics. A survey among farmers revealed persistent challenges, such as the unavailability of transport services, a lack of monitoring, and weak communication with logistics providers. An ICT-enabled framework integrating GPS, RFID, wireless sensor networks, and cloud-based web services is proposed to address these issues. The findings highlight how smart logistics can improve efficiency, reduce risk, and enhance real-time decision-making, ultimately benefiting both farmers and consumers.

We live in a digitally connected world inspired by state-of-the-art ICT technologies and networks, inasmuch as the use of digital gadgets and apps is exponentially increasing in all domains of life. In parallel, artificial intelligence has evolved as an essential tool in all sorts of applications and systems such as healthcare systems. Healthcare is the key domain where the use of ICT infrastructure, technologies and artificial intelligence are playing a major role in providing connected and personalized digital health experiences. The vision is to provide intelligent and customized digital health solutions and involve the masses in personal health monitoring. This research proposes AiDHealth as an intelligent personal health monitoring framework based on artificial intelligence for healthcare data analytics and connectivity for personal health monitoring. AiDHealth relies on various machine learning and deep learning models for achieving prediction accuracy in healthcare data analytics. The extensive Pima Indian Diabetes (PID) dataset has been used for investigation. The findings of our experiments illustrate the effectiveness and suitability of the suggested MLPD model. AdaBoost classifier performance has the highest accuracy in prediction when calculated to the individual classifiers. The AdaBoost classifier produced the best accuracy i.e., 0.975%. The results reveal improvements to state-of-the-art procedures in the proposed model. Next, we trained the models and produced a 10-fold cross-validation illness risk index for each sample. Our findings suggest a need for greater experiments to compare the above-mentioned machine learning methods. We identified the AdaBoost classifier and Decision Tree classifiers with the best prediction with an average of 0.975% and a work Curve Area (AUC) of 0.994%. Thus, because the design of the AdaBoost classifier is superior, it can forecast the danger of type 2 diabetes more accurately than the existing algorithms and lead to intelligent prevention and control of diabetes.