Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq-7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.

The use of FPGA based system on chip SoCs to implement controllers for Power Electronics applications is becoming increasingly popular. This is mainly due to the flexibility that allows to have in the same device a processor able to execute high level control algorithms, and a programmable logic where complex algorithms can be hardware accelerated. This hardware implementation is usually carried out using HLS tools. All this complexity makes the design and verification tasks difficult. HW/SW co-simulation has proven to be a very efficient technique to fulfil this challenging SoC designs. Simulation speed is a critical feature and is mainly limited by the processor simulator, especially when the device has several cores, as it happens with MultiProcessor SoCs (MPSoC). In this case, using a very fast processor simulator, such as QEMU, is crucial to achieve reasonable simulation speed. This work describes Virtual Platform based on QEMU, SystemC and HLS to co-simulate hardware and software designs in a fast way. A smart-switcher design for synchronization of micro-grids is taken as case study. It controls the connection of a micro-grid to mains when both of them have similar voltage and phase. It includes a dual PLL, implemented in HW, that provides all the information to the control algorithm executed in the processor. The simulation speed of the proposed Virtual Platform is analyzed under different working conditions and compared with other solutions.