Medical imaging is considered one of the most important advances in the history of medicine and has become an essential part of the diagnosis and treatment of patients. Earlier prediction and treatment have been driving the acquisition of higher image resolutions as well as the fusion of different modalities, raising the need for sophisticated hardware and software systems for medical image registration, storage, analysis, and processing. In this scenario and given the new clinical pipelines and the huge clinical burden of hospitals, these systems are often required to provide both highly accurate and real-time processing of large amounts of imaging data. Additionally, lowering the prices of each part of imaging equipment, as well as its development and implementation, and increasing their lifespan is crucial to minimize the cost and lead to more accessible healthcare. This paper focuses on the evolution and the application of different hardware architectures (namely, CPU, GPU, DSP, FPGA, and ASIC) in medical imaging through various specific examples and discussing different options depending on the specific application. The main purpose is to provide a general introduction to hardware acceleration techniques for medical imaging researchers and developers who need to accelerate their implementations.

The massive deployment of smart meters in most Western countries in recent decades has allowed the creation and development of a significant variety of applications, mainly related to efficient energy management. The information provided about energy consumption has also been dedicated to the areas of social work and health. In this context, smart meters are considered single-point non-intrusive sensors that might be used to monitor the behaviour and activity patterns of people living in a household. This work describes the design of a short-term behavioural alarm generator based on the processing of energy consumption data coming from a commercial smart meter. The device captured data from a household for a period of six months, thus providing the consumption disaggregated per appliance at an interval of one hour. These data were used to train different intelligent systems, capable of estimating the predicted consumption for the next one-hour interval. Four different approaches have been considered and compared when designing the prediction system: a recurrent neural network, a convolutional neural network, a random forest, and a decision tree. By statistically analysing these predictions and the actual final energy consumption measurements, anomalies can be detected in the undertaking of three different daily activities: sleeping, breakfast, and lunch. The recurrent neural network achieves an F1-score of 0.8 in the detection of these anomalies for the household under analysis, outperforming other approaches. The proposal might be applied to the generation of a short-term alarm, which can be involved in future deployments and developments in the field of ambient assisted living.

Non-Intrusive Load Monitoring (NILM) techniques are commonly used to measure and identify the power consumption of different types of household appliances, starting from an aggregated signal obtained from a single measurement point. Currently, they are often based on the extended deployment of smart meters (SM) carried out in most developed countries in the last decade. Based on the measurements acquired by SMs, it is possible to disaggregate energy consumption, and then to identity the corresponding loads plugged to the mains of a house or building. NILM techniques can be applied in different application fields, such as energy efficiency, active demand response management, or even as a way to infer the behaviour patterns of the people living in a certain household under monitoring, in the context of Ambient Intelligence for Independent Living (AIIL). This paper presents a new approach for energy disaggregation through the use of Recurrent Neural Networks (RNN) based on measurements from a single point at low sampling rates. The proposed framework takes the power signals acquired by an SM as inputs, then pre-processes and detects the on/off switching events of the different appliances considered, and finally classifies them using two different Long Short Term Memory (LSTM)-based topologies. The proposal validation is carried out through the use of the well-known public dataset Building Level fUlly labelled for Electricity Disaggregation (BLUED). Several configurations of classification topologies have been compared, obtaining an average classification accuracy in the experimental results that exceeds 85%.

Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq-7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.

This work presents the CODEUS platform, which includes a simulation tool together with an online experimental demonstrator to offer analysis and testing flexibility for researchers and developers in Ultrasonic Indoor Positioning Systems (UIPSs). The simulation platform allows most common encoding techniques and sequences to be tested in a configurable UIPS. It models the signal modulation and processing, the ultrasonic transducers’ response, the beacon distribution, the channel propagation effects, the synchronism, and the application of different positioning algorithms. CODEUS provides results and performance analysis for different metrics and at different stages of the signal processing. The UIPS simulation tool is specified by means of the MATLAB© App-Designer environment, which enables the definition of a user-friendly interface. It has also been linked to an online demonstrator that can be managed remotely by means of a website, thus avoiding any hardware requirement or equipment on behalf of researchers. This demonstrator allows the selected transmission schemes, modulation or encoding techniques to be validated in a real UIPS, therefore enabling a fast and easy way of carrying out experimental tests in a laboratory environment, while avoiding the time-consuming tasks related to electronic design and prototyping in the UIPS field. Both simulator and online demonstrator are freely available for researchers and students through the corresponding website.