Machine learning is widely used for building data-driven models that are highly useful for optimization. In this study, a finite element model-based adaptive machine learning method is presented for chip package reliability prediction and design optimization. This machine learning method employs a validated multi-scale finite element model for training data generation. An adaptive sampling scheme is developed to optimize the training process with a steepest descent algorithm. The developed method was used to optimize ultra low-k chip package design. The effects of ten key design parameters on chip packaging reliability were considered. Multiple machine learning algorithms were evaluated for model development. It is shown that the adaptive sampling method performs much better than existing sequential sampling methods and that the finite element-based machine learning model can be used to achieve improved prediction accuracy for chip package design optimization.

Multilevel finite element analysis (FEA) was used to study the effects of wiring density and solder pillar structure on chip-package interaction (CPI) for advanced Cu/low k mixed-signal chips. The mixed signal chip has analog and digital wiring designs with different metal densities, incorporating extreme low-k (ELK), low-k (LK) and oxide dielectrics in 10 wiring layers. The results are compared with uniform signal chips with uniform metal density on each wiring layer. The first principal stress was found to increase by 1.5 to 3x in the mixed signal chip between the analog and the isolation channel of the ELK and LK layers due to the different wiring density. In addition, the energy release rate (ERR) was significantly increased to reach a critical ERR ratio higher than 1 to drive interfacial delamination, raising serious chip-package interaction (CPI) reliability concern for the mixed signal chip. The results were attributed to the Dundurs effect due to the material mismatch and the nonuniform metal density in the mixed signal chip. In the study of the pillar structure effect, intermetallic compound (IMC) growth was found to be important and can substantially increase the critical ERR ratio to degrade the CPI reliability of the mixed signal chip.

Graphene has attracted enormous research interest due to its extraordinary material properties. Process control to achieve high quality graphene is indispensable to graphene-based applications. This research investigates interaction effects of process parameters affecting graphene quality in the low-pressure chemical vapor deposition (LPCVD) process. A fractional factorial design of experiment for factor analysis is conducted to provide understanding on not only main process parameters, but also the interaction among them. Graphene quality including the number of layers and grain size is analyzed. To achieve monolayer graphene with larger grain size, a condition with low CH₄/H₂ ratio, short growth time, high growth pressure, high growth temperature, and slow cooling rate is recommended. This study considers a large set of process parameters and their interaction effects and provides guidelines to optimize graphene growth via LPCVD focusing on the number of graphene layers and the grain size.

Purpose: The purpose of this study is to analyze the short-term development pattern and long-term development trend of the digital supply chain.Design/methodology/approach: This study uses the combination of short-term game and long-term evolutionary game theory.Findings: Findings of this study suggest that irrational decisions can make the evolutionary path of the digital supply chain complex and unpredictable.Originality/value: This study proposes an evolutionary game model for the digital supply chain that can provide good guidance for the digitalization process of enterprises.

New analytical methods are proposed to investigate the warpage of 2.5D system in package (SIP) fabricated through different temperature steps based on laminate theories. The solutions apply in both axisymmetric and rectangular configurations for packages with different multilayer sections. A multi-step finite element (FE) model is developed to verify the analytical results and to examine stress distributions in the chip-package structures with respect to the fabrication steps. The analytical and FE results are in good agreement to account for the warpage at the chip scale, whereas the FE model provides local stress analysis at the micro-bump and solder ball levels that can be further extended for failure analysis.