Experimental characterization of the damage induced to SiC power MOSFETs by heavy-ion irradiation is presented as a premise to a finite element simulation study aimed at gaining an insight into the physics of damage formation. Thanks to the new experimental setup, which is capable of accurately measuring the time evolution of the gate and drain leakage currents during irradiation, we herein demonstrate that the gate of a SiC power MOSFET is damaged by heavy-ion irradiation at biasing drain voltages lower than 100 V, which is less than 10% of the nominal blocking voltage of the tested devices. The evolution of the gate and drain leakage currents during irradiation is explained considering that localized resistive paths due to damage sites are formed across the gate oxide. The results presented herein indicate the strong sensitivity of SiC power MOSFETs to gate rupture even if the main concern in the literature addressed so far is the rupture of the drain structure due to single-event burnout.

This article presents the results of a 2-D finite element simulation study of the gate damages induced by heavy-ion irradiation in SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs). The time evolution of the electric field in the gate oxide is studied. Two effects are investigated: the first is associated with the charge deposition in the SiC portion of the MOSFET, with the time evolution studied using the 2-D finite element simulator; the second one results from holes generated during the ion transit, trapped in the gate oxide after the fast electrons have been quickly swept away by the electric field. Two different techniques have been combined for estimating the hole concentration in the gate oxide: the well-known recombination rate was modified to consider the trapped charge yield, as was recently done to better interpret single event gate rupture (SEGR) failure of silicon power MOSFETs. Under ion irradiation test conditions at which the gate damage experimentally starts to be observed, we demonstrate that, because of the ion impact, regardless of the ion linear energy transfer (LET), the peak value of the electric field in the gate oxide becomes practically equal to the oxide breakdown field (~12-15 MV/cm). Moreover, we show that simulations can be used to predict the test conditions at which gate damage starts to appear as a function of LET and the range of heavy ions used in the irradiation experiments.

Soft switching for both primary and secondary side devices is available by using LLC converters. This resonant converter is an ideal candidate for today’s high frequency, high efficiency, and high power density applications like adapters, Uninterrupted Power Supplies (UPS), Solid State Transformers (SST), electric vehicle battery chargers, renewable energy systems, servers, and telecom systems. Using Gallium-Nitride (GaN)-based power switches in this converter merits more and more switching frequency, power density, and efficiency. Therefore, the present paper focused on GaN-based LLC resonant converters. The converter structure, operation regions, design steps, and drive system are described precisely. Then its losses are discussed, and the magnets and inductance characteristics are investigated. After that, various interleaved topologies, as a solution to improve power density and decrease current ripples, have been discussed. Also, some challenges and concerns related to GaN-based LLC converters have been reviewed. Commercially available power transistors based on various technologies, i.e., GaN HEMT, Silicon (Si) MOSFET, and Silicon Carbide (SiC) have been compared. Finally, the LLC resonant converter has been simulated by taking advantage of LTspice and GaN HEMT merits, as compared with Si MOSFETs.

The purpose of this paper is to present a detailed experimental and numerical study on the mechanisms involved in Insulated Gate Bipolar Transistor (IGBT) instability during turn-ON short circuit that can compromise its robustness in particular load and driving conditions. It is shown that the IGBT may exhibit oscillations at both low and high frequencies depending on different physical mechanisms. Furthermore, a new methodology that allows determining the stability limits of the device in relation with the parameters of the external circuit is proposed. The experimental measurements confirm the obtained results.

The use of a resistive shunt is one of the simplest and most used methods for measuring current in an electronic device. Many researchers use this method to measure drain current during short-circuiting of fast devices such as GaN HEMTs. However, the high switching speed of these devices together with the non-ideality of the shunt resistors produces an overestimation of the current in the initial phases of the transient. In this paper, a passive compensation network is proposed, which is formed by adding an inductor to the voltage measurement circuit and allows an accurate measurement of the current using the resistive shunt even in the presence of very fast devices. The proposed method is validated by simulations and experimental measurements.