Soft switching for both primary and secondary side devices is available by using LLC converters. This resonant converter is an ideal candidate for today’s high frequency, high efficiency, and high power density applications like adapters, Uninterrupted Power Supplies (UPS), Solid State Transformers (SST), electric vehicle battery chargers, renewable energy systems, servers, and telecom systems. Using Gallium-Nitride (GaN)-based power switches in this converter merits more and more switching frequency, power density, and efficiency. Therefore, the present paper focused on GaN-based LLC resonant converters. The converter structure, operation regions, design steps, and drive system are described precisely. Then its losses are discussed, and the magnets and inductance characteristics are investigated. After that, various interleaved topologies, as a solution to improve power density and decrease current ripples, have been discussed. Also, some challenges and concerns related to GaN-based LLC converters have been reviewed. Commercially available power transistors based on various technologies, i.e., GaN HEMT, Silicon (Si) MOSFET, and Silicon Carbide (SiC) have been compared. Finally, the LLC resonant converter has been simulated by taking advantage of LTspice and GaN HEMT merits, as compared with Si MOSFETs.

The use of a resistive shunt is one of the simplest and most used methods for measuring current in an electronic device. Many researchers use this method to measure drain current during short-circuiting of fast devices such as GaN HEMTs. However, the high switching speed of these devices together with the non-ideality of the shunt resistors produces an overestimation of the current in the initial phases of the transient. In this paper, a passive compensation network is proposed, which is formed by adding an inductor to the voltage measurement circuit and allows an accurate measurement of the current using the resistive shunt even in the presence of very fast devices. The proposed method is validated by simulations and experimental measurements.

Temperature is a critical parameter for the GaN HEMT as it sharply impacts the electrical characteristics of the device more than for SiC or Si MOSFETs. Either when designing a power converter or testing a device for reliability and robustness characterizations, it is essential to estimate the junction temperature of the device. For this aim, manufacturers provide compact models to simulate the device in SPICE-based simulators. These models provide the junction temperature, which is considered uniform along the channel. We demonstrate through two-dimensional numerical simulations that this approach is not suitable when the device undergoes high electrothermal stress, such as during short circuit (SC), when the temperature distribution along the channel is strongly not uniform. Based on numerical simulations and experimental measurements on a 650 V/4 A GaN HEMT, we derived a thermal network suitable for SPICE simulations to correctly compute the junction temperature and the SC current, even if not providing information about the possible failure of the device due to the formation of a local hot spot. For this reason, we used a second thermal network to estimate the maximum temperature reached inside the device, whose results are in good agreement with the experimental observed failures.

Gallium Nitride (GaN) transistors are gaining popularity in industrial and automotive applications due to their ability to achieve high power density and higher efficiency. However, their reliability and robustness still pose limitations to their widespread adoption. Short-Circuit (SC) robustness has been widely studied in literature by means of experimental characterizations. However, less attention has been drawn to the simulation of GaN HEMTs operating in SC conditions due to the absence of accurate models that can fully describe the main phenomena impacting the SC behavior of a GaN device, such as drain current collapse and gate-leakage current increasing. In this context, this work proposes a behavioral model for the drain and gate current of a 650-V/60-A GaN HEMT, that is integrated into the manufacturer model of the device in the LTSpice simulation environment. The proposed model shows a valuable accuracy improvement in determining drain and gate currents during the SC of a GaN half-bridge, as demonstrated by comparing simulations and experimental tests performed on a hardware prototype in different operating conditions. It is also demonstrated that the model can be applied to other 650 V GaN HEMTs, becoming a reliable instrument to simulate the device and to design an effective SC protection circuit.

Gallium Nitride (GaN) transistors are gaining popularity in industrial and automotive applications due to their ability to achieve high power density and higher efficiency. However, their reliability and robustness still pose limitations to their widespread adoption. Short-Circuit (SC) robustness has been widely studied in literature by means of experimental characterizations. However, less attention has been drawn to the simulation of GaN HEMTs operating in SC conditions due to the absence of accurate models that can fully describe the main phenomena impacting the SC behavior of a GaN device: such as drain current collapse and gate-leakage current increasing. In this context, this work proposes a behavioral model for the 650-V/60-A GaN HEMT, which includes both drain and gate current.The obtained drain and gate current equations were implemented and integrated into the manufacturer model of the device in the simulation environment. The proposed behavioral model is validated experimentally by means of LTSpice simulations and experimental SC results on a half-bridge hardware prototype composed of two GaN devices at different DC-link voltages. The main outcomes demonstrate a valuable accuracy improvement in comparison with the manufacturer model.