Ferroelectric capacitors (FeCAPs) with high process compatibility, high reliability, ultra-low programming current and fast operation speed are promising candidates to traditional volatile and nonvolatile memory. In addition, they have great potential in the fields of storage, computing, and memory logic. Nevertheless, effective methods to realize logic and memory in FeCAP devices are still lacking. This study proposes a 1T2C FeCAP-based in situ bitwise X(N)OR logic based on a charge-sharing function. First, using the 1T2C structure and a two-step write-back circuit, the nondestructive reading is realized with less complexity than the previous work. Second, a method of two-line activation is used during the operation of X(N)OR. The verification results show that the speed, area and power consumption of the proposed 1T2C FeCAP-based bitwise logic operations are significantly improved.

Von Neumann computing architecture system has the characteristic of high energy consumption and slow speed due to the memory bottlenecks of hardware platforms when it processes computing tasks that rely on big data. The drawbacks of memory bottlenecks in traditional structures can be improved significantly using PIM (processing-in-memory) architectures. FeRAM (ferroelectric memory) is a novel memory with the advantages of simple structure, high integration and low power consumption. Thus, it has always been considered as one of the most proper memories for PIM. In this paper, FeRAM was designed as memory and converted to basic computing cells, based on its charge sharing function. A mechanism of two-line activation was adopted during the process of X(N)OR. Then, peripheral circuits were moderately modified to implement bit-by-bit X(N)OR operations between operands stored in the same bit line. Besides, the simulation of X(N)OR logic was carried out. The final simulation results show that the speed, area and power consumption of current FeRAM-based logic operations are improved. The research can be used to enhance the performance of arithmetic logic units for future PIM.