Atomic scale control of the thickness of thin film makes atomic layer deposition highly advantageous in the preparation of high quality super-lattices. However, precisely controlling the film chemical stoichiometry is very challenging. In this study, we deposited SiO_x film with different stoichiometry by plasma enhanced atomic layer deposition. After reviewing various deposition parameters like temperature, precursor pulse time, and gas flow, the silicon dioxides of stoichiometric (SiO₂) and non-stoichiometric (SiO_1.8 and SiO_1.6) were successfully fabricated. X-ray photo-electron spectroscopy was first employed to analyze the element content and chemical bonding energy of these films. Then the morphology, structure, composition, and optical characteristics of SiO_x film were systematically studied through atomic force microscope, transmission electron microscopy, X-ray reflection, and spectroscopic ellipsometry. The experimental results indicate that both the mass density and refractive index of SiO_1.8 and SiO_1.6 are less than SiO₂ film. The energy band-gap is approved by spectroscopic ellipsometry data and X-ray photo-electron spectroscopy O 1s analysis. The results demonstrate that the energy band-gap decreases as the oxygen concentration decreases in SiO_x film. After we obtained the Si-rich silicon oxide film deposition, the SiO_1.6/SiO₂ super-lattices was fabricated and its photoluminescence (PL) property was characterized by PL spectra. The weak PL intensity gives us greater awareness that more research is needed in order to decrease the x of SiO_x film to a larger extent through further optimizing plasma-enhanced atomic layer deposition processes, and hence improve the photoluminescence properties of SiO_x/SiO₂ super-lattices.

Non-volatile computing-in-memory (nvCIM) can potentially meet the ever-increasing demands on improving the energy efficiency (EF) for intelligent edge devices. However, it still suffers from limited input parallelism due to the parasitic effects, signal margin degradation due to device non-idealities, and large hardware cost for analog readout. In this work, we present a two-transistor-one-resistor (2T1R) resistive memory (RRAM) nvCIM macro featuring: 1) a macro structure with decoupled memory and computing data paths; 2) the weighted hybrid 2T1R (WH-2T1R) cell array; 3) the redundant sub-array mapping scheme of the most-significant-bit (RSM-MSB); and 4) reference-subtracting current sense amplifier (RS-CSA). A test-chip is silicon-verified using the 28-nm high-k/metal-gate (HKMG) logic process with foundry-developed RRAM. The test-chip performs linear analog multiply-and-accumulate (MAC) operations over 32 accumulation channels and achieves 30.34–154.04 TOPS/W with 1-bit input (IN), 3-bit weight (W), and 4-bit output (O). Evaluations with the ResNet-18 model show that the MSB-RSM scheme results in 0.96% and 2.83% improvement on CIFAR-10 and CIFAR-100 inference accuracy, respectively.

Edge artificial intelligence systems require higher frequency due to intensive computational demands, while most traditional entropy sources decay with frequency. This work shows the physical properties of the Fe-diode devices are ideal for edge systems with high frequencies and dramatic temperature changes. The noise density of Fe-diode can be modified by the amplitude of the read voltage and remains stable at high frequencies and temperature fluctuations. A Bayesian neural network with Fe-diode devices is experimentally implemented in high-speed, high-density silicon-based chips. This hierarchical Bayesian neural network is demonstrated on 3D 16-layer Fe-diode array based on unified entropy source and 4-state synapse. Properties including high area efficiency, wide working temperature range, low energy in-situ training, high recognition accuracy are finally achieved.

Resistive random-access memory (RRAM) based non-volatile computing-in-memory (nvCIM) has been regarded as a promising solution to enable efficient data-intensive artificial intelligence (AI) applications on resource-limited edge systems. However, existing weighted-current summation-based nvCIM suffers from device non-idealities and significant time, storage, and energy overheads when processing high-precision analog signals. To address these issues, we propose a 3T2R digital nvCIM macro for a fully hardware-implemented binary convolutional neural network (HBCNN), focusing on accelerating edge AI applications at low weight precision. By quantizing the voltage-division results of RRAMs through inverters, the 3T2R macro provides a stable rail-to-rail output without analog-to-digital converters or sensing amplifiers. Moreover, both batch normalization and sign activation are integrated on-chip. The hybrid simulation results show that the proposed 3T2R digital macro achieves an 86.2% (95.6%) accuracy on the CIFAR-10 (MNIST) dataset, corresponding to a 4.7% (1.9%) accuracy loss compared to the software baselines, which also feature a peak energy efficiency of 51.3 TOPS/W and a minimum latency of 8 ns, realizing an energy-efficient, low-latency, and robust AI processor.

Probabilistic computing is an emerging computational paradigm that uses probabilistic circuits to efficiently solve optimization problems such as invertible logic, where traditional digital computations are difficult to solve. This paper proposes a true random number generator (TRNG) based on resistive random-access memory (RRAM), which is combined with an activation function implemented by a piecewise linear function to form a standard p-bit cell, one of the most important parts of a p-circuit. A p-bit multiplexing strategy is also applied to reduce the number of p-bits and improve resource utilization. To verify the superiority of the proposed probabilistic circuit, we implement the invertible p-circuit on a field-programmable gate array (FPGA), including AND gates, full adders, multi-bit adders, and multipliers. The results of the FPGA implementation show that our approach can significantly save the consumption of hardware resources.

Hf $_{0.5}$ Zr $_{0.5}$ O $_{2}$ (HZO)-based ferroelectric random access memory (FeRAM) is a good candidate for the embedded nonvolatile memory (eNVM) applications because of its high reliability, high speed, good scalability, and process compatibility with logic large-scale integrated circuits (LSIs). However, challenges still exist in designing robust read/write circuits for high reliability and sufficient read yield. This work presents a 9-Mb (8 $+$ 1-Mb error correcting code (ECC)) HZO-based nonvolatile FeRAM chip with high-performance read and write peripheral circuits. A TiN/HZO/TiN ferroelectric capacitor (FeCAP) is integrated in the back-end-of-line of a 130-nm CMOS process with a 700-nm-diameter capacitor and a mega-level capacity. A temperature-aware ECC-assisted write driver (ECC-WD) is designed to improve the reliability and power efficiency of FeRAM. The offset-canceled sense amplifier (SA) and a dummy-based reference generator are designed to tolerate a small bitline (BL) signal margin and to reduce the read bit-error rate (BER). Measurement results show 2 $\times$ remnant polarization ( $P_{r}$ ) $>$ 30 $\mu $ C/cm $^{2}$ , $>$ 10 $^{12}$ -cycle endurance, 7-ns write and 5-ns read time, sub-3-V operating voltage, and 10-year data retention at 85 $^{\circ}$ C.