The current-voltage $\left(I\text{−}V\right)$ characteristics and resistance switching mechanism of $\mathrm{Ag}∕{\mathrm{La}}_{0.7}{\mathrm{Ca}}_{0.3}{\mathrm{MnO}}_3\left(\mathrm{LCMO}\right)∕\mathrm{Pt}$ sandwiched films, which were deposited on $\mathrm{Pt}∕\mathrm{Ti}∕{\mathrm{SiO}}_2∕\mathrm{Si}$ substrates by pulse laser deposition, were investigated. The $I\text{−}V$ characteristics can be explained by hole carrier injected space charge limited (SCL) conduction controlled by $\mathrm{Ag}∕\mathrm{LCMO}$ interface traps exponentially distributed in energy. The hysteresis and asymmetry in the $I\text{−}V$ curves are due to trapping/detrapping process of hole carriers. The resistance changes under different voltage range are related to the carrier trapping levels induced by the positive voltage bias. Retention property of resistance is attributed to ordering/disordering transition, which is discussed on the basis of trap-assisted interface phase separation scenario. Therefore, the resistance switching induced by voltage pulses is attributed to the interface induced bulklike limited transport effect.

Memory devices with high speed and high density are highly desired to address the ‘memory wall’ issue. Here we demonstrated a highly scalable, three-dimensional stackable ferroelectric diode, with its rectifying polarity modulated by the polarization reversal of Hf_0.5Zr_0.5O₂ films. By visualizing the hafnium/zirconium lattice order and oxygen lattice order with atomic-resolution spherical aberration-corrected STEM, we revealed the correlation between the spontaneous polarization of Hf_0.5Zr_0.5O₂ film and the displacement of oxygen atom, thus unambiguously identified the non-centrosymmetric Pca2₁ orthorhombic phase in Hf_0.5Zr_0.5O₂ film. We further implemented this ferroelectric diode in an 8 layers 3D array. Operation speed as high as 20 ns and robust endurance of more than 10⁹ were demonstrated. The built-in nonlinearity of more than 100 guarantees its self-selective property that eliminates the need for external selectors to suppress the leakage current in large array. This work opens up new opportunities for future memory hierarchy evolution.

Monolayer molybdenum disulfide (ML-MoS₂) is an emergent two-dimensional (2D) semiconductor holding potential for flexible integrated circuits (ICs). The most important demands for the application of such ML-MoS₂ ICs are low power consumption and high performance. However, these are currently challenging to satisfy due to limitations in the material quality and device fabrication technology. In this work, we develop an ultra-thin high-κ dielectric/metal gate fabrication technique for the realization of thin film transistors based on high-quality wafer scale ML-MoS₂ on both rigid and flexible substrates. The rigid devices can be operated in the deep-subthreshold regime with low power consumption and show negligible hysteresis, sharp subthreshold slope, high current density, and ultra-low leakage currents. Moreover, we realize fully functional large-scale flexible ICs operating at voltages below 1 V. Our process could represent a key step towards using energy-efficient flexible ML-MoS₂ ICs in portable, wearable, and implantable electronics.