Probabilistic computing is an emerging computational paradigm that uses probabilistic circuits to efficiently solve optimization problems such as invertible logic, where traditional digital computations are difficult to solve. This paper proposes a true random number generator (TRNG) based on resistive random-access memory (RRAM), which is combined with an activation function implemented by a piecewise linear function to form a standard p-bit cell, one of the most important parts of a p-circuit. A p-bit multiplexing strategy is also applied to reduce the number of p-bits and improve resource utilization. To verify the superiority of the proposed probabilistic circuit, we implement the invertible p-circuit on a field-programmable gate array (FPGA), including AND gates, full adders, multi-bit adders, and multipliers. The results of the FPGA implementation show that our approach can significantly save the consumption of hardware resources.

In recent years, Ising machines have emerged as a promising hardware solution for tackling combinatorial optimization problems (COPs). However, existing Ising solvers, whether based on discrete-time or continuous-time approaches, often face challenges in balancing solution quality, scalability, and computational speed. Discrete-time solvers typically suffer from slow convergence due to the sequential nature of spin updates, while continuous-time solvers often lack effective annealing mechanisms, limiting their solution accuracy. To address these limitations, this work proposes a novel architecture that integrates a differential Resistive Random Access Memory (RRAM) cell-based Ising design with a Randomized Granular Update (RAGU) method. This approach enhances scalability to larger spin systems while maintaining robust performance against circuit non-idealities and device variations. Additionally, an adaptive bitline (BL) voltage clamper is incorporated into the read path to limit current magnitudes, significantly improving power efficiency. A key feature of the RAGU method is its ability to naturally introduce randomness during the update process through coarse-grained updates, serving as an imprecise but effective sampling mechanism. This innovation not only accelerates convergence and improves the system’s ability to escape local minima but also ensures high solution quality. Extensive simulations and experiments on randomly weighted graphs with varying densities demonstrate that the proposed architecture consistently achieves near-optimal solutions (>96%) while drastically reducing the time-to-solution to as low as $0.6~\mu $ s.

The neuromorphic system aims to implement large-scale spiking neural networks (SNN) through hardware, ultimately achieving human-level intelligence. At this stage, it is difficult for a single silicon-based chip to reach the density of the human brain, so it is important to improve the area efficiency of neuromorphic chips. We present a novel neuromorphic hardware that employs high area-efficiency chain RRAM synaptic array, and compact RRAM-based neurons. The proposed chain RRAM structure achieves a small cell size of 41.5F2 at 28 nm logic process. Compared to the conventional 1T1R structure, the chain structure has a 22.2% area reduction and a 58.8% parasitic capacitance reduction. As for the neuron design, we use RRAM instead of the capacitor to integrate membrane voltage. To alleviate the endurance issue of RRAM, we propose an (anti-) integration scheme that removes the operation of membrane voltage reset. The simulation results demonstrate an average energy consumption of 1.15pJ per spike and an area of $15.9\mu $ m2. With the (anti-)integration scheme, the RRAM’s lifetime is demonstrated to extend by $2\times $ and the energy of programming RRAM is demonstrated to be reduced by $2\times $ .

The long-time retention issue of resistive random access memory (RRAM) presents a significant challenge in maintaining the performance of large-scale RRAM-based computation-in-memory (CIM) systems. To address the long-term inference accuracy degradation caused by RRAM instability, we proposed a combined forming strategy, which can effectively suppress resistance drift and improve inference accuracy without periodic updates of RRAM cells. With this optimized strategy, the probability of high resistance state (HRS) drift was reduced to 5%, and the inference accuracy could be maintained at 88% even after 105s at 125°. This work provided a valuable strategy for enhancing devices retention and sustaining accuracy in RRAM-based CIM systems.

Hafnium-based ferroelectric memories are a promising approach to enhancing integrated circuit performance, offering advantages such as miniaturization, compatibility with CMOS technology, fast read and write speeds, non-volatility, and low power consumption. However, FeRAM (Ferroelectric Random Access Memory) still faces challenges related to endurance and retention susceptibility to process variations. Hence, testing and obtaining the core parameters of ferroelectric capacitors continuously is essential to investigate these phenomena and explore the potential solution. The traditional method for measuring ferroelectric capacitors has limitations in timing generation capability, introduces parasitic capacitance, and lacks accuracy for small-area capacitors. In this study, we analyzed the working principle of ferroelectric capacitors and designed a method to detect the remnant polarization, saturation polarization, and imprint offset of ferroelectric capacitors. Further, we further proposed a circuit implementation method. The proposed test circuit conquers these limitations and enables high-precision testing of ferroelectric capacitors, contributing to developing hafnium-based ferroelectric memories. The circuit includes a flip-readout circuit, a capacitance calibration circuit, and a voltage-to-time converter and time-to-digital converter (VTC&TDC) readout circuit. According to simulation results, the capacitance calibration circuit reduces the deviation of the capacitance by 84%, and the accuracy of the readout circuit is 5.91 bits, with a readout time of 150 ns and a power consumption of 1 mW. This circuit enables low-cost acquisition of array-level small-area ferroelectric capacitance data, which can guide subsequent device optimization and circuit design.