Single-photon avalanche diodes (SPADs) have become the sensor of choice in many applications whenever high sensitivity, low noise, and sharp timing performance are required, simultaneously. Recently, SPADs designed in CMOS technology, have yielded moderately good performance in these parameters, but never equaling their counterparts fabricated in highly customized, non-standard technologies. The arguments in favor of CMOS-compatible SPADs were miniaturization, cost and scalability. In this paper, we present the first CMOS SPAD with performance comparable or better than that of the best custom SPADs, to date. The SPAD-based design, fully integrated in 180 nm CMOS technology, achieves a peak photon detection probability (PDP) of 55% at 480 nm with a very broad spectrum spanning from near ultraviolet (NUV) to near infrared (NIR) and a normalized dark count rate (DCR) of 0.2 cps/ $\mu$ m $^2$ , both at 6 V of excess bias. Thanks to a dedicated CMOS pixel circuit front-end, an afterpulsing probability of about 0.1% at a dead time of $\sim$ 3 ns were achieved. We designed three SPADs with a diameter of 25, 50, and 100 $\mu$ m to study the impact of size on the timing jitter and to create a scaling law for SPADs. For these SPADs, a single-photon time resolution (SPTR) of 12.1 ps, 16 ps, and 27 ps (FWHM) was achieved at 6 V of excess bias, respectively. The SPADs operate in a wide range of temperatures, from −65 $^{\circ }$ C to 40 $^{\circ }$ C, reaching a normalized DCR of 1.6 mcps/ $\mu$ m $^2$ at 6 V of excess bias for the 25 $\mu$ m at −65 $^{\circ }$ C. The proposed SPADs are ideal for a wide range of applications, including (quantum) LiDAR, super-resolution microscopy, quantum random number generators, quantum key distribution, fluorescence lifetime imaging, time-resolved Raman spectroscopy, to name a few. All these applications can take advantage of the vastly improved performance of our detectors, while enjoying the opportunities of megapixel resolutions promised by the economy of scale that is offered by CMOS technologies.

CMOS single-photon avalanche diodes (SPADs) have broken into the mainstream by enabling the adoption of imaging, timing, and security technologies in a variety of applications within the consumer, medical and industrial domains. The continued scaling of technology nodes creates many benefits but also obstacles for SPAD-based systems. Maintaining and/or improving upon the high-sensitivity, low-noise, and timing performance of demonstrated SPADs in custom technologies or well-established CMOS image sensor processes remains a challenge. In this paper, we present SPADs based on DPW/BNW junctions in a standard Bipolar-CMOS-DMOS (BCD) technology with results comparable to the state-of-the-art in terms of sensitivity and noise in a deep sub-micron process. Technology CAD (TCAD) simulations demonstrate the improved PDP with the simple addition of a single existing implant, which allows for an engineered performance without modifications to the process. The result is an 8.8 $\mu$ m diameter SPAD exhibiting $\sim$ 2.6 cps/ $\mu$ m $^2$ DCR at 20 $^{\circ}$ C with 7 V excess bias. The improved structure obtains a PDP of 62% and $\sim$ 4.2% at 530 nm and 940 nm, respectively. Afterpulsing probability is $\sim$ 0.97% and the timing response is 52 ps FWHM when measured with integrated passive quench/active recharge circuitry at 3 V excess bias.

Major advances in silicon pixel detectors, with outstanding timing performance, have recently attracted significant attention in the community. In this work we present and discuss the use of state-of-the-art Geiger-mode APDs, also known as single-photon avalanche diodes (SPADs), for the detection of minimum ionizing particles (MIPs) with best-in-class timing resolution. The SPADs were implemented in standard CMOS technology and integrated with on-chip quenching and recharge circuitry. Two devices in coincidence allowed to measure the time-of-flight of 180 GeV/c momentum pions with a coincidence time resolution of 22 ps FWHM (9.4 ps Gaussian sigma). Radiation hardness measurements, also presented here, highlight the suitability of this family of devices for a wide range of high energy physics (HEP) applications.

Quantum random number generators (QRNGs) are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in order to produce a random string. In integrated designs, there is often little modeling or analytical description of the entropy source, circuit extraction, and post-processing provided. In this work, we present a single-photon avalanche diode (SPAD)-based QRNG design, which utilizes the quantum random flip-flop (QRFF) method. Extensive modeling of detector and circuit imperfections that result in entropy degradation is performed. A new method to analytically model serial autocorrelations of the proposed bit generation method, which includes detector dead time, is proposed. Then, a Verilog-AMS model is developed in order to validate the analytical model in simulation. A novel transistor implementation of the QRFF circuit is presented, which enables compensation of the degradation in entropy inherent to the finite non-symmetric transitions of the random flip-flop. Finally, a full system containing two independent arrays of the QRFF circuit is manufactured and tested in a 55-nm bipolar–CMOS–DMOS (BCD) technology node, demonstrating bit generation statistics that are commensurate to the developed model. The full chip is able to generate 3.3 Gb/s of data when operated with an external LED. Pixelwise and spatial analysis of bias and correlation is performed. NIST STS (SP 800-22) and SP 800-90B are used to benchmark the generated bit strings.

Scintillators play a key role in the detection chain of several applications which rely on the use of ionizing radiation, and it is often mandatory to extract and detect the generated scintillation light as efficiently as possible. Typical inorganic scintillators do however feature a high index of refraction, which impacts light extraction efficiency in a negative way. Furthermore, several applications such as preclinical Positron Emission Tomography (PET) rely on pixelated scintillators with small pitch. In this case, applying reflectors on the crystal pixel surface, as done conventionally, can have a dramatic impact of the packing fraction and thus the overall system sensitivity. This paper presents a study on light extraction techniques, as well as combinations thereof, for two of the most used inorganic scintillators (LYSO and BGO). Novel approaches, employing Distributed Bragg Reflectors (DBRs), metal coatings, and a modified Photonic Crystal (PhC) structure, are described in detail and compared with commonly used techniques. The nanostructure of the PhC is surrounded by a hybrid organic/inorganic silica sol-gel buffer layer which ensures robustness while maintaining its performance unchanged. We observed in particular a maximum light gain of about 41% on light extraction and 21% on energy resolution for BGO, a scintillator which has gained interest in the recent past due to its prompt Cherenkov component and lower cost.

We present an analog silicon photomultiplier (SiPM) based on a standard 55-nm Bipolar-CMOS-DMOS (BCD) technology. The SiPM is composed of 16 × 16 single-photon avalanche diodes (SPADs) and measures 0.29 × 0.32 mm$^{2}$. Each SPAD cell is passively quenched by a monolithically integrated 3.3 V thick oxide transistor. The measured gain is 3.4 × 10$^{5}$ at 5 V excess bias voltage. The single-photon timing resolution (SPTR) is 185 ps and the multi-photon timing resolution (MPTR) is 120 ps at 3.3 V excess bias voltage. We integrate the SiPM into a co-axial light detection and ranging (LiDAR) system with a time-correlated single-photon counting (TCSPC) module in FPGA. The depth measurement up to 25 m achieves an accuracy of 2 cm and precision of 2 mm under the room ambient light condition. With co-axial scanning, the intensity and depth images of complex scenes with resolutions of 128 × 256 and 256 × 512 are demonstrated. The presented SiPM enables the development of cost-effective LiDAR system-on-chip (SoC) in the advanced technology.