Thermal boundary resistance (TBR) is a key property for the thermal management of high power micro- and opto-electronic devices and for the development of high efficiency thermal barrier coatings and thermoelectric materials. Prediction of TBR is important for guiding the discovery of interfaces with very low or very high TBR. In this study, we report the prediction of TBR by the machine learning method. We trained machine learning models using the collected experimental TBR data as training data and materials properties that might affect TBR as descriptors. We found that the machine learning models have much better predictive accuracy than the commonly used acoustic mismatch model and diffuse mismatch model. Among the trained models, the Gaussian process regression and the support vector regression models have better predictive accuracy. Also, by comparing the prediction results using different descriptor sets, we found that the film thickness is an important descriptor in the prediction of TBR. These results indicate that machine learning is an accurate and cost-effective method for the prediction of TBR.

We propose a planar device architecture compatible with the CMOS process technology as the optimal current benchmark of a Si-nanowire (NW) thermoelectric (TE) power generator. The proposed device is driven by a temperature gradient that is formed in the proximity of a perpendicular heat flow to the substrate. Therefore, unlike the conventional TE generators, the planar short Si-NWs need not be suspended on a cavity structure. Under an externally applied temperature difference of 5 K, the recorded TE power density is observed to be $12~\mu \text{W}$ /cm ² by shortening the Si-NWs length and suppressing the parasitic thermal resistance of the Si substrate. The demonstration paves a pathway to develop cost-effective autonomous internet-of-things applications that utilize the environmental and body heats.

Wide-bandgap gallium nitride (GaN)-based semiconductors offer significant advantages over traditional Si-based semiconductors in terms of high-power and high-frequency operations. As it has superior properties, such as high operating temperatures, high-frequency operation, high breakdown electric field, and enhanced radiation resistance, GaN is applied in various fields, such as power electronic devices, renewable energy systems, light-emitting diodes, and radio frequency (RF) electronic devices. For example, GaN-based high-electron-mobility transistors (HEMTs) are used widely in various applications, such as 5G cellular networks, satellite communication, and radar systems. When a current flows through the transistor channels during operation, the self-heating effect (SHE) deriving from joule heat generation causes a significant increase in the temperature. Increases in the channel temperature reduce the carrier mobility and cause a shift in the threshold voltage, resulting in significant performance degradation. Moreover, temperature increases cause substantial lifetime reductions. Accordingly, GaN-based HEMTs are operated at a low power, although they have demonstrated high RF output power potential. The SHE is expected to be even more important in future advanced technology designs, such as gate-all-around field-effect transistor (GAAFET) and three-dimensional (3D) IC architectures. Materials with high thermal conductivities, such as silicon carbide (SiC) and diamond, are good candidates as substrates for heat dissipation in GaN-based semiconductors. However, the thermal boundary resistance (TBR) of the GaN/substrate interface is a bottleneck for heat dissipation. This bottleneck should be reduced optimally to enable full employment of the high thermal conductivity of the substrates. Here, we comprehensively review the experimental and simulation studies that report TBRs in GaN-on-SiC and GaN-on-diamond devices. The effects of the growth methods, growth conditions, integration methods, and interlayer structures on the TBR are summarized. This study provides guidelines for decreasing the TBR for thermal management in the design and implementation of GaN-based semiconductor devices.

For harvesting energy from waste heat, the power generation densities and fabrication costs of thermoelectric generators (TEGs) are considered more important than their conversion efficiency because waste heat energy is essentially obtained free of charge. In this study, we propose a miniaturized planar Si-nanowire micro-thermoelectric generator (SiNW-μTEG) architecture, which could be simply fabricated using the complementary metal–oxide–semiconductor–compatible process. Compared with the conventional nanowire μTEGs, this SiNW-μTEG features the use of an exuded thermal field for power generation. Thus, there is no need to etch away the substrate to form suspended SiNWs, which leads to a low fabrication cost and well-protected SiNWs. We experimentally demonstrate that the power generation density of the SiNW-μTEGs was enhanced by four orders of magnitude when the SiNWs were shortened from 280 to 8 μm. Furthermore, we reduced the parasitic thermal resistance, which becomes significant in the shortened SiNW-μTEGs, by optimizing the fabrication process of AlN films as a thermally conductive layer. As a result, the power generation density of the SiNW-μTEGs was enhanced by an order of magnitude for reactive sputtering as compared to non-reactive sputtering process. A power density of 27.9 nW/cm² has been achieved. By measuring the thermal conductivities of the two AlN films, we found that the reduction in the parasitic thermal resistance was caused by an increase in the thermal conductivity of the AlN film and a decrease in the thermal boundary resistance.