In the traditional virtual flux estimation for a three-phase pulsewidth modulation rectifier, the integration element causes problems for the initial value and dc bias, and the unstable grid voltage induces a nonconstant flux amplitude. To address these issues, an improved direct power control scheme based on an adaptive sliding mode observer is proposed in this work. The observer employs a sigmoid function as switch function to estimate the grid-side source voltage. Meanwhile, an adaptive compensator instead of pure integral element is also designed to dynamically adjust compensation. The stability of this observer is proved by the Lyapunov function; moreover, simulations and experimental results indicate that this new virtual flux observer substantially improves the observation accuracy based on voltage sensorless control. The application of this strategy successfully suppresses the fluctuation of the dynamic voltage response in the dc bus, eliminating high-frequency noise from the grid side, while simultaneously boosting the power quality.

The dc-link voltage fluctuation caused by the change of working state of the load motor has been one of the key issues in the pulse width modulation rectifier-inverter system. In this study, an improved model predictive control (MPC) scheme is proposed to address this problem. The MPC is applied to both the rectifier stage and the inverter stage in the system. Direct power control is used in the rectifier stage and the direct torque control is employed in the inverter stage, with the key novelty of the active power reference values being defined by both real-time and periodic compensation power based on the system-level power-balance model. Meanwhile, an MPC algorithm based on a two-step prediction is introduced to compensate for the delay of a digital controller. Comparison has been conducted between the proposed scheme and three other methods. Simulation and experimental results show that the proposed control scheme exhibits good performance in both the rectifier stage and the inverter stage with improved dynamic response and suppressed voltage fluctuation of the dc-link voltage.

This article presents a novel strategy for designing weighting factors in the model predictive control (MPC) of a three-level inverter-fed permanent magnet synchronous motor (PMSM) by combining multi-objective particle swarm optimization (MOPSO) and artificial neural network (ANN). A cost function containing three weighting factors is designed to formulate a multi-objective optimization scheme. The MOPSO algorithm is employed to establish the Pareto front and calculate the optimal weighting factors for each operating condition. Additionally, an ANN is introduced for online tuning of the optimal weighting factors. Simulation and experimental results demonstrate that the proposed control scheme can solve the design problem of weighting factors, meet the real-time requirements of the inverter system, and exhibit excellent dynamic and steady performance.

Optimized production scheduling can greatly improve efficiency and reduce waste in the steel manufacturing industry. With the increasing demands on the economy, the environment, and society, more and more factors need to be considered in the production scheduling process. Currently, only a few methods are developed for the comprehensive evaluation and prioritization of scheduling schemes. This paper proposes a novel MCGDM (multi-criteria group decision making) method for the ranking and selection of production scheduling schemes. First, a novel indicator system involving both qualitative and quantitative indicators is put forward. Diverse statistical methods and evaluation functions are proposed for the evaluation of quantitative indicators. The evaluation method of qualitative indicators is proposed based on heterogeneous data, cloud model theory, and group decision-making techniques. Then, a novel Group AHP model is proposed to determine the weights of all evaluation indicators. Finally, a novel cloud-model-enhanced TOPSIS (technique for order of preference by similarity to ideal solution) method is proposed to rank alternative production scheduling schemes. A practical example is presented to show the implementation details and demonstrate the feasibility of our proposed method. The results and comparative analysis indicate that our hybrid MCGDM method is more reasonable, flexible, practical, and effective in evaluating and ranking production scheduling schemes in an uncertain environment.

In this paper, we present a successive approximation register (SAR) analog-to-digital converter (ADC) with a charge-pump (CP) phase-locked loop (PLL) and a bootstrapped switch, also called PLL-SAR ADC. To meet system-on-chip (SOC) and industrial requirements, the proposed SAR ADC and the control circuits of electric vehicles must be integrated into a single chip and be fabricated using the TSMC 0.25-μm 1P3M complementary metal oxide semiconductor (CMOS) high-voltage process. It is difficult to implement a high-speed SAR ADC with the TSMC 0.25-μm CMOS high-voltage process because it includes an N-type buried layer, which shorts all p-type metal oxide semiconductor field-effect transistor (PMOSFET) bodies together to withstand high voltages. In the proposed PLL-SAR ADC, two clock signals, an external clock signal and an internal clock signal from the CP-PLL, are provided to guarantee that a correct clock signal is fed. This design improves the robustness of the designed system. A monotonic capacitor-switching procedure is considered to reduce power consumption. Furthermore, a bootstrapped switch was added along with a dummy switch and a dummy transistor to eliminate disturbances in the input voltages and to improve the device’s anti-noise capability. Moreover, a two-stage dynamic comparator was used to prevent kickback noise induced by the parasitic capacitors. The measurements indicate that the signal-to-noise-and-distortion ratio, effective number of bits, power consumption, and chip area are 53.82 dB, 8.65 bits, 1.256 mW, and 1.261 × 0.975 mm², respectively. The FoM is approximately 0.625 pJ/conv-step at 1.256 mW, 8.65 bits, and 5 MS/s. The high sampling rate of 5 MS/s and high accuracy of 8.65 bits are the main advantages of the proposed PLL-SAR ADC.