Chaotic systems, especially hyper-chaotic systems are suitable for digital image encryption because of their complex properties such as pseudo randomness and extreme sensitivity. This paper proposes a new color image encryption algorithm based on a hyper-chaotic system constructed by a tri-valued memristor. The encryption process is based on the structure of permutation-diffusion, and the transmission of key information is realized through hyper-chaotic synchronization technology. In this design, the hash value of the plaintext image is used to generate the initial key the permutation sequence with the Hash table structure based on the hyper-chaotic sequence is used to implement pixel-level and bit-level permutation operations. Hilbert curves combining with the ciphertext feedback mechanism are applied to complete the diffusion operation. A series of experimental analyses have been applied to measure the novel algorithm, and the results show that the scheme has excellent encryption performance and can resist a variety of attacks. This method can be applied in secure image communication fields.

Memristors and memcapacitors are two new nonlinear elements with memory. In this paper, we present a Hewlett-Packard memristor model and a charge-controlled memcapacitor model and design a new chaotic oscillator based on the two models for exploring the characteristics of memristors and memcapacitors in nonlinear circuits. Furthermore, many basic dynamical behaviors of the oscillator, including equilibrium sets, Lyapunov exponent spectrums, and bifurcations with various circuit parameters, are investigated theoretically and numerically. Our analysis results show that the proposed oscillator possesses complex dynamics such as an infinite number of equilibria, coexistence oscillation, and multi-stability. Finally, a discrete model of the chaotic oscillator is given and the main statistical properties of this oscillator are verified via Digital Signal Processing chip experiments and National Institute of Standards and Technology tests.

This paper presents a series of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Prior demonstrations of memristive logic are typically constrained to single-stage logic due to the variety of challenges that affect device performance. Noise accumulation across subsequent stages can be amortized by integrating ternary logic gates, thus enabling higher density data transmission, where more complex computation can take place within a smaller number of stages when compared to single-bit computation. We present the design of a ternary half adder, a ternary full adder, a ternary multiplier, and a ternary magnitude comparator. These designs are simulated in SPICE using the broadly accessible Knowm memristor model, and we perform experimental validation of individual stages using an in-house fabricated Si-doped HfO _x memristor which exhibits low cycle-to-cycle variation, and thus contributes to robust long-term performance. We ultimately show an improvement in data density in each logic block of between $5.2\times - 17.3\times $ , which also accounts for intermediate voltage buffering to alleviate the memristive loading problem.