Emerging applications such as the Internet-of-Things and more-electric aircraft require electronics with integrated data storage that can operate in extreme temperatures with high energy efficiency. As transistor leakage current increases with temperature, nanoelectromechanical relays have emerged as a promising alternative. However, a reliable and scalable non-volatile relay that retains its state when powered off has not been demonstrated. Part of the challenge is electromechanical pull-in instability, causing the beam to snap in after traversing a section of the airgap. Here we demonstrate an electrostatically actuated nanoelectromechanical relay that eliminates electromechanical pull-in instability without restricting the dynamic range of motion. It has several advantages over conventional electrostatic relays, including low actuation voltages without extreme reduction in critical dimensions and near constant actuation airgap while the device moves, for improved electrostatic control. With this nanoelectromechanical relay we demonstrate the first high-temperature non-volatile relay operation, with over 40 non-volatile cycles at 200 ^∘C.

Active gate driving of power devices seeks to shape switching trajectories via the gate, for example to reduce EMI without degrading efficiency. To this end, driver ICs with integrated arbitrary waveform generators have been used to achieve complex gate signals. In this paper, we describe for the first time the implementation details of a digitally programmable arbitrary waveform gate driver capable of a 10 GHz waypoint rate, including comprehensive design considerations for critical high-speed subsystems that codify the trade-off in flexibility, speed and area. Our design, which is taped out in a 180 nm high-voltage CMOS process, utilises buffers that switch up to ten times in a single clock cycle to overcome the limited achievable clock-speed of high-voltage silicon integrated circuits, and a fully digital architecture to provide robustness under high slew-rates of the ground rail. The driver IC has networks of 100 ps delay elements that are digitally configured prior to a switching transient, to selectively control an array of fast, parallel-connected drivers with different output impedances. Key to the high timing resolution are high-speed asynchronous circuits for memory readout, output buffering and pulse generation. The driver IC is experimentally evaluated to have a 100 ps resolution, and to operate reliably in a 400 V GaN bridge leg, under ground-rail voltage slew rates peaking at over 100 V/ns. Design rules are provided to obtain an architecture with the least area for a given set of timing and impedance resolution requirements. The reported design methods enable complex driving waveforms to be applied during nanosecond-scale transients of GaN power devices and demonstrate how digitally-programmable active gate drivers for GaN power FETs can be designed to meet a given set of application requirements.

The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect. An FPGA built entirely from nanoelectromechanical (NEM) relays can effectively eliminate leakage energy losses, reduce the interconnect dynamic energy, operate at temperatures > 225 °C and tolerate radiation doses in excess of 100 Mrad, while hybrid FPGAs comprising both complementary metal-oxide-semiconductor (CMOS) transistors and NEM relays (NEM-CMOS) have the potential to realise improvements in performance and energy efficiency. Largescale integration of NEM relays, however, poses a significant engineering challenge due to the presence of moving parts. We discuss the design of FPGAs utilising NEM relays based on a heterogeneous 3-D integration scheme, and carry out a scaling study to quantify key metrics related to performance and energy efficiency in both NEM-only and NEM-CMOS FPGAs. We show how the integration scheme has a profound effect on these metrics by changing the length of global wires. The scaling regime beyond which net performance and energy benefits is seen in NEMCMOS over a baseline 90 nm CMOS technology is defined by an effective relay beam length of 0.5 μm, on-resistance of 200 kΩ, and a via pitch of 0.4 μm, all achievable with existing process technology. For ultra-low energy applications that are not performance critical, NEM-only FPGAs can provide close to 15× improvement in energy efficiency.

Nowadays, electronics face a challenge regarding the power consumption of integrated circuits (ICs). There is a need for new devices that can provide improved switching capabilities. The downscaled electrostatically actuated ohmic switch, as a (re)emerging device, is a promising candidate to meet this need. To bring such a device seamlessly into IC design, it must be accompanied by an accurate, fast and robust analytical compact model. The development and the main characteristics of such a model are described within this paper. Extensive numerical simulations and measurements have been used to validate the model.

Diverse areas such as the Internet of Things (IoT), aerospace and industrial electronics increasingly require non-volatile memory to work under high-temperature, radiation-hard conditions, with zero standby power. Nanoelectromechanical (NEM) relays uniquely have the potential to work at 300 °C and absorb high levels of radiation, with zero leakage current across the entire operational range. While NEM relays that utilise stiction for non-volatile operation have been demonstrated, it is not clear how to design a relay to reliably achieve given programming and reprogramming voltages, an essential requirement in producing a memory. Here, we develop an analytical, first-principle physics-based model of rotational NEM relays to provide detailed understanding of how the programming and reprogramming voltages vary based on the device dimensions and surface adhesion force. We then carry out an experimental parametric study of relays with a critical dimension of $\approx ~\mathrm {80~~\, \text {n} \text {m} }$ to characterise the surface adhesion force, and derive guidelines for how a NEM relay should be dimensioned for a given contact surface force, feature size constraints and operating requirements. We carry out a scaling study to show that voltages of $\approx ~\mathrm {1~~\, \text {V}}$ and a footprint under $\approx ~\mathrm {2~~\, \mu \text {m} ^{2}}$ can be achieved with a critical dimension of $\approx ~\mathrm {10~~\, \text {n} \text {m} }$ , with this device architecture. [2021-0138]