In this paper, the dc electrothermal behavior of InGaP/GaAs HBT test devices and arrays for power amplifier output stages is extensively analyzed through an efficient simulation approach. The approach relies on a full circuit representation of the domains, which accounts for electrothermal effects through the thermal equivalent of the Ohm’s law and can be solved in any commercial circuit simulator. In particular, the power-temperature feedback is described through an equivalent thermal network automatically obtained by (i) generating a realistic 3-D geometry/mesh of the domain in the environment of a numerical tool with the aid of an in-house routine; (ii) feeding the geometry/mesh to FANTASTIC, which extracts the network without performing simulations. Nonlinear thermal effects adversely affecting the behavior of devices/arrays at high temperatures are included through a calibrated Kirchhoff’s transformation. For the test devices, the thermally-induced distortion in I–V curves is explained, and the limits of the safe operating regions are identified for a wide range of bias conditions. A deep insight into the electrothermal behavior of the arrays is then provided, with particular emphasis on the detrimental nonuniform operation. Useful guidelines are offered to designers in terms of layout and choice of the ballasting strategy.

This paper presents a comprehensive overview of nonlinear thermal effects in bipolar transistors under static conditions. The influence of these effects on the thermal resistance is theoretically explained and analytically modeled using the single-semiconductor assumption. A detailed review of experimental techniques to extract the thermal resistance as a function of backside temperature and/or dissipated power from DC measurements is provided; advantages, underlying approximations, and limitations of all methods are clarified, and guidelines for their correct application are given. Accurate FEM thermal simulations of an InGaP/GaAs and a Si/SiGe HBT are performed to verify the accuracy of the single-semiconductor theory. The thermal resistance formulations employed in the most popular compact bipolar transistor models for circuit simulators are investigated, and it is found that they do not properly describe nonlinear thermal effects. Alternative implementations of the more accurate single-semiconductor theory are then proposed for the future versions of the compact models.

This paper presents a commercial or industrial view of III-V compact models for circuit design. We contrast the requirements of III-V modeling to those of silicon. The differences in requirements are strongly rooted in the applications that III-V devices are used in the end user of III-V models and the differences in the ``ecosystems'' of the technologies. These differences create both challenges and opportunity for the III-V modeling community.

This paper presents a critical and detailed overview of experimental techniques for the extraction of the thermal resistance of bipolar transistors from simple DC current/voltage measurements. More specifically, this study focuses on techniques based on a thermometer, i.e., the relation between the base-emitter voltage and the junction temperature. The theory behind the techniques is described with a unified and comprehensible nomenclature. Advantages, underlying approximations, and limitations of the methods are illustrated. The accuracy is assessed by emulating the DC measurements with PSPICE electrothermal simulations of a transistor model, applying the techniques to the simulated currents/voltages, and comparing the extracted thermal resistance data with the values obtained from the target formulation embedded in the transistor model. An InGaP/GaAs HBT and an Si/SiGe HBT for high-frequency applications are considered as case-studies.

An extensive electrothermal analysis of current mirrors fabricated in silicon-on-glass and GaAs bipolar technologies is presented. Experimental results demonstrate that pronounced electrothermal effects may arise, which lead not only to a poor mirroring action, but also to a thermal instability occurrence for the output transistor. A simple relation is derived for predicting the instability onset Circuit and numerical simulations are employed to provide a deep insight into the underlying physics and suggest alternative solutions to counteract the electrothermal feedback.

As frequencies increase, the use of smaller value metal-insulator-metal (MIM) capacitors increases. For small capacitors, errors due to the bias (as fabricated to as drawn difference) of the top plate can cause significant errors. This bias is not correctly monitored with resistance based W (RLWB) monitors and can be made worse if the resistive based RLWB is used. We present a simple capacitive based technique that uses only two test capacitors to determine the value of the capacitive linewidth bias (CLWB) that is more appropriate for use electromagnetic (EM) simulation and provides consistency with typical MIM compact models.