Keni Qiu

Dr. Keni Qiu

Information Engineering College, Capital Normal University, Beijing 100048, China
orcid

Research Focus & Metrics

Academic Career Length

12Years (2015-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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4 February 2023 in Electronics
Verified
Journal Article
Open access
PDF file
XCXuena Chen
Xuena Chen
LSLi Su
Li Su
JZJinxiu Zhao
Jinxiu Zhao
Keni QiuKeni Qiu
Keni Qiu
Na JiangNa Jiang
Na Jiang
GZGuang Zhai
Guang Zhai
Sign language recognition has been utilized in human–machine interactions, improving the lives of people with speech impairments or who rely on nonverbal instructions. Thanks to its higher temporal resolution, less visual redundancy information and lower energy consumption, the use of an event camera with a new dynamic vision sensor (DVS) shows promise with regard to sign language recognition with robot perception and intelligent control. Although previous work has focused on event camera-based, simple gesture datasets, such as DVS128Gesture, event camera gesture datasets inspired by sign language are critical, which poses a great impediment to the development of event camera-based sign language recognition. An effective method to extract spatio-temporal features from event data is significantly desired. Firstly, the event-based sign language gesture datasets are proposed and the data have two sources: traditional sign language videos to event stream (DVS_Sign_v2e) and DAVIS346 (DVS_Sign). In the present dataset, data are divided into five classification, verbs, quantifiers, position, things and people, adapting to actual scenarios where robots provide instruction or assistance. Sign language classification is demonstrated in spike neuron networks with a spatio-temporal back-propagation training method, leading to the best recognition accuracy of 77%. This work paves the way for the combination of event camera-based sign language gesture recognition and robotic perception for the future intelligent systems.

27 January 2023 in ACM Transactions on Embedded Computing Systems
Verified
Journal Article
Open access
YLYueting Li
Yueting Li
WKWang Kang
Wang Kang
KZKunyu Zhou
Kunyu Zhou
Keni QiuKeni Qiu
Keni Qiu
WZWeisheng ZHAO
Weisheng ZHAO
Energy consumption has been a big challenge for electronic devices, particularly for battery-powered Internet of Things (IoT) equipment. To address such a challenge, on the one hand, low-power electronic design methodologies and novel power management techniques have been proposed, such as nonvolatile memories and instantly on/off systems; on the other hand, the energy harvesting technology by collecting signals from human activity or the environment has attracted widespread attention in the IoT area. However, the system with self-powered energy harvesting may suffer frequent energy failures or fluctuating energy conditions, which degrade system reliability and user experience. Therefore, how to make the system under unreliable power inputs operate correctly and efficiently is one of the most critical issues for energy harvesting technology. In this article, we built an instantly on/off system based on nonvolatile STT-MRAM for IoT applications, which can instantly power on/off under different conditions of the harvested energy. The system powers on and operates normally when the harvested energy is enough (over the preset threshold); otherwise, the system powers off and stores the operational data back to the nonvolatile STT-MRAM. We described implementations of the hardware/software co-designed architecture (with image acquisition as an example) based on the commercialized 32 MB STT-MRAM, and we experimentally demonstrated the system functionality and efficiency under five typical energy harvesting scenarios, including radio frequency, thermal, solar, piezoelectric, and WIFI. Our experimental results show that the power consumption and data restore time were reduced by 15.1% and 714 times, respectively, in comparison with the DRAM-based counterpart.

25 April 2024 in ACM Transactions on Embedded Computing Systems
Verified
Journal Article
Open access
YLYueting Li
Yueting Li
XWXueyan Wang
Xueyan Wang
HZHe Zhang
He Zhang
BPBiao Pan
Biao Pan
Keni QiuKeni Qiu
Keni Qiu
WZWeisheng Zhao
Weisheng Zhao
Convolutional Neural Networks (CNNs) have significantly impacted embedded system applications across various domains. However, this exacerbates the real-time processing and hardware resource-constrained challenges of embedded systems. To tackle these issues, we propose spin-transfer torque magnetic random-access memory (STT-MRAM)-based near memory computing (NMC) design for embedded systems. We optimize this design from three aspects: Fast-pipelined STT-MRAM readout scheme provides higher memory bandwidth for NMC design, enhancing real-time processing capability with a non-trivial area overhead. Direct index compression format in conjunction with digital sparse matrix-vector multiplication (SpMV) accelerator supports various matrices of practical applications that alleviate computing resource requirements. Custom NMC instructions and stream converter for NMC systems dynamically adjust available hardware resources for better utilization. Experimental results demonstrate that the memory bandwidth of STT-MRAM achieves 26.7 GB/s. Energy consumption and latency improvement of digital SpMV accelerator are up to 64× and 1,120× across sparsity matrices spanning from 10% to 99.8%. Single-precision and double-precision elements transmission increased up to 8× and 9.6×, respectively. Furthermore, our design achieves a throughput of up to 15.9× over state-of-the-art designs.

1 October 2017
Verified
Conference Paper
Closed access
PCPatrick Cronin
Patrick Cronin
CYChengmo Yang
Chengmo Yang
DZDongqin Zhou
Dongqin Zhou
Keni QiuKeni Qiu
Keni Qiu
XSXin Shi
Xin Shi
Yongpan LiuYongpan Liu
Yongpan Liu
As the Internet of Things (IoT) gravitates towards small sensors and connected devices in all areas of our everyday lives, ultra low power computation has taken center stage as an important factor in realizing this goal. While power-sipping architectures have been designed, battery technology struggled to keep up, both in size and weight, adding unnecessary bulk to current generation IoT implementations. Fortunately, non-volatile processors (NVPs) have been proposed to bridge the gap between low power architectures and respond to the issue of unstable power supplies. Meanwhile, the non-volatile nature of the processor introduces a multitude of heretofore unseen security issues not present in current volatile architectures. This paper explores the landscape of current NVP architectures and the security areas that should be addressed before NVPs are selected as the platform of choice for low power IoT applications. Four security threats related to NVP's non-volatility, checkpoint system, timer and power are examined. The paper furthermore proposes three strategies to enhance NVP security, including secure checkpoint, voltage logging, and arrhythmic heartbeats and amnesia avoidance.

1 January 2019 in Microelectronics Journal
Verified
Journal Article
Closed access
Keni QiuKeni Qiu
Keni Qiu
YZYujie Zhu
Yujie Zhu
YXYuanchao Xu
Yuanchao Xu
QHQirun Huo
Qirun Huo
CXChun Jason Xue
Chun Jason Xue

16 October 2018 in Sustainable Computing: Informatics and Systems
Verified
Journal Article
Closed access
ZGZhiyao Gong
Zhiyao Gong
Keni QiuKeni Qiu
Keni Qiu
WCWeiwen Chen
Weiwen Chen
YNYuanhui Ni
Yuanhui Ni
YXYuanchao Xu
Yuanchao Xu
JYJianlei Yang
Jianlei Yang